11251e490SNobuhiro Iwamatsu /* 21251e490SNobuhiro Iwamatsu * board/renesas/koelsch/koelsch.c 31251e490SNobuhiro Iwamatsu * 41251e490SNobuhiro Iwamatsu * Copyright (C) 2013 Renesas Electronics Corporation 51251e490SNobuhiro Iwamatsu * 61251e490SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 71251e490SNobuhiro Iwamatsu * 81251e490SNobuhiro Iwamatsu */ 91251e490SNobuhiro Iwamatsu 101251e490SNobuhiro Iwamatsu #include <common.h> 111251e490SNobuhiro Iwamatsu #include <malloc.h> 12*0bf51cb0SNobuhiro Iwamatsu #include <dm.h> 13*0bf51cb0SNobuhiro Iwamatsu #include <dm/platform_data/serial_sh.h> 141251e490SNobuhiro Iwamatsu #include <asm/processor.h> 151251e490SNobuhiro Iwamatsu #include <asm/mach-types.h> 161251e490SNobuhiro Iwamatsu #include <asm/io.h> 171251e490SNobuhiro Iwamatsu #include <asm/errno.h> 181251e490SNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 191251e490SNobuhiro Iwamatsu #include <asm/gpio.h> 201251e490SNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 2144e1eebfSNobuhiro Iwamatsu #include <asm/arch/rcar-mstp.h> 2290362c0cSNobuhiro Iwamatsu #include <netdev.h> 2390362c0cSNobuhiro Iwamatsu #include <miiphy.h> 241251e490SNobuhiro Iwamatsu #include <i2c.h> 25ccde6771SNobuhiro Iwamatsu #include <div64.h> 261251e490SNobuhiro Iwamatsu #include "qos.h" 271251e490SNobuhiro Iwamatsu 281251e490SNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 291251e490SNobuhiro Iwamatsu 30ccde6771SNobuhiro Iwamatsu #define CLK2MHZ(clk) (clk / 1000 / 1000) 311251e490SNobuhiro Iwamatsu void s_init(void) 321251e490SNobuhiro Iwamatsu { 33ec9b386eSNobuhiro Iwamatsu struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 34ec9b386eSNobuhiro Iwamatsu struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 35ccde6771SNobuhiro Iwamatsu u32 stc; 361251e490SNobuhiro Iwamatsu 371251e490SNobuhiro Iwamatsu /* Watchdog init */ 381251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 391251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 401251e490SNobuhiro Iwamatsu 41ccde6771SNobuhiro Iwamatsu /* CPU frequency setting. Set to 1.5GHz */ 42ccde6771SNobuhiro Iwamatsu stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 43ccde6771SNobuhiro Iwamatsu clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 44ccde6771SNobuhiro Iwamatsu 451251e490SNobuhiro Iwamatsu /* QoS */ 461251e490SNobuhiro Iwamatsu qos_init(); 471251e490SNobuhiro Iwamatsu } 481251e490SNobuhiro Iwamatsu 491251e490SNobuhiro Iwamatsu #define TMU0_MSTP125 (1 << 25) 501251e490SNobuhiro Iwamatsu #define SCIF0_MSTP721 (1 << 21) 5190362c0cSNobuhiro Iwamatsu #define ETHER_MSTP813 (1 << 13) 5290362c0cSNobuhiro Iwamatsu 531251e490SNobuhiro Iwamatsu int board_early_init_f(void) 541251e490SNobuhiro Iwamatsu { 551251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 561251e490SNobuhiro Iwamatsu 571251e490SNobuhiro Iwamatsu /* SCIF0 */ 581251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 591251e490SNobuhiro Iwamatsu 6090362c0cSNobuhiro Iwamatsu /* ETHER */ 6190362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 6290362c0cSNobuhiro Iwamatsu 631251e490SNobuhiro Iwamatsu return 0; 641251e490SNobuhiro Iwamatsu } 651251e490SNobuhiro Iwamatsu 6690362c0cSNobuhiro Iwamatsu /* LSI pin pull-up control */ 6790362c0cSNobuhiro Iwamatsu #define PUPR5 0xe6060114 6890362c0cSNobuhiro Iwamatsu #define PUPR5_ETH 0x3FFC0000 6990362c0cSNobuhiro Iwamatsu #define PUPR5_ETH_MAGIC (1 << 27) 701251e490SNobuhiro Iwamatsu int board_init(void) 711251e490SNobuhiro Iwamatsu { 721251e490SNobuhiro Iwamatsu /* adress of boot parameters */ 73956556fbSNobuhiro Iwamatsu gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 741251e490SNobuhiro Iwamatsu 751251e490SNobuhiro Iwamatsu /* Init PFC controller */ 761251e490SNobuhiro Iwamatsu r8a7791_pinmux_init(); 771251e490SNobuhiro Iwamatsu 7890362c0cSNobuhiro Iwamatsu /* ETHER Enable */ 7990362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 8090362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RX_ER, NULL); 8190362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RXD0, NULL); 8290362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RXD1, NULL); 8390362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_LINK, NULL); 8490362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_REFCLK, NULL); 8590362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_MDIO, NULL); 8690362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TXD1, NULL); 8790362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TX_EN, NULL); 8890362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TXD0, NULL); 8990362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_MDC, NULL); 9090362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_IRQ0, NULL); 9190362c0cSNobuhiro Iwamatsu 9290362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 9390362c0cSNobuhiro Iwamatsu gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 9490362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 9590362c0cSNobuhiro Iwamatsu 9690362c0cSNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_5_22, 0); 9790362c0cSNobuhiro Iwamatsu mdelay(20); 9890362c0cSNobuhiro Iwamatsu gpio_set_value(GPIO_GP_5_22, 1); 9990362c0cSNobuhiro Iwamatsu udelay(1); 10090362c0cSNobuhiro Iwamatsu 1011251e490SNobuhiro Iwamatsu return 0; 1021251e490SNobuhiro Iwamatsu } 1031251e490SNobuhiro Iwamatsu 10490362c0cSNobuhiro Iwamatsu #define CXR24 0xEE7003C0 /* MAC address high register */ 10590362c0cSNobuhiro Iwamatsu #define CXR25 0xEE7003C8 /* MAC address low register */ 10690362c0cSNobuhiro Iwamatsu int board_eth_init(bd_t *bis) 10790362c0cSNobuhiro Iwamatsu { 10890362c0cSNobuhiro Iwamatsu #ifdef CONFIG_SH_ETHER 10990362c0cSNobuhiro Iwamatsu int ret = -ENODEV; 11090362c0cSNobuhiro Iwamatsu u32 val; 11190362c0cSNobuhiro Iwamatsu unsigned char enetaddr[6]; 11290362c0cSNobuhiro Iwamatsu 11390362c0cSNobuhiro Iwamatsu ret = sh_eth_initialize(bis); 11490362c0cSNobuhiro Iwamatsu if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 11590362c0cSNobuhiro Iwamatsu return ret; 11690362c0cSNobuhiro Iwamatsu 11790362c0cSNobuhiro Iwamatsu /* Set Mac address */ 11890362c0cSNobuhiro Iwamatsu val = enetaddr[0] << 24 | enetaddr[1] << 16 | 11990362c0cSNobuhiro Iwamatsu enetaddr[2] << 8 | enetaddr[3]; 12090362c0cSNobuhiro Iwamatsu writel(val, CXR24); 12190362c0cSNobuhiro Iwamatsu 12290362c0cSNobuhiro Iwamatsu val = enetaddr[4] << 8 | enetaddr[5]; 12390362c0cSNobuhiro Iwamatsu writel(val, CXR25); 12490362c0cSNobuhiro Iwamatsu 12590362c0cSNobuhiro Iwamatsu return ret; 12690362c0cSNobuhiro Iwamatsu #else 12790362c0cSNobuhiro Iwamatsu return 0; 12890362c0cSNobuhiro Iwamatsu #endif 12990362c0cSNobuhiro Iwamatsu } 13090362c0cSNobuhiro Iwamatsu 1311251e490SNobuhiro Iwamatsu int dram_init(void) 1321251e490SNobuhiro Iwamatsu { 1331251e490SNobuhiro Iwamatsu gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 1341251e490SNobuhiro Iwamatsu 1351251e490SNobuhiro Iwamatsu return 0; 1361251e490SNobuhiro Iwamatsu } 1371251e490SNobuhiro Iwamatsu 13890362c0cSNobuhiro Iwamatsu /* koelsch has KSZ8041NL/RNL */ 13990362c0cSNobuhiro Iwamatsu #define PHY_CONTROL1 0x1E 14090362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE 0xC0000 14190362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE_ACK 0x4000 14290362c0cSNobuhiro Iwamatsu int board_phy_config(struct phy_device *phydev) 14390362c0cSNobuhiro Iwamatsu { 14490362c0cSNobuhiro Iwamatsu int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 14590362c0cSNobuhiro Iwamatsu ret &= ~PHY_LED_MODE; 14690362c0cSNobuhiro Iwamatsu ret |= PHY_LED_MODE_ACK; 14790362c0cSNobuhiro Iwamatsu ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 14890362c0cSNobuhiro Iwamatsu 14990362c0cSNobuhiro Iwamatsu return 0; 15090362c0cSNobuhiro Iwamatsu } 15190362c0cSNobuhiro Iwamatsu 1521251e490SNobuhiro Iwamatsu const struct rmobile_sysinfo sysinfo = { 1531251e490SNobuhiro Iwamatsu CONFIG_RMOBILE_BOARD_STRING 1541251e490SNobuhiro Iwamatsu }; 1551251e490SNobuhiro Iwamatsu 1561251e490SNobuhiro Iwamatsu void reset_cpu(ulong addr) 1571251e490SNobuhiro Iwamatsu { 158b8f383b8SNobuhiro Iwamatsu u8 val; 159b8f383b8SNobuhiro Iwamatsu 160b8f383b8SNobuhiro Iwamatsu i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 161b8f383b8SNobuhiro Iwamatsu i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 162b8f383b8SNobuhiro Iwamatsu val |= 0x02; 163b8f383b8SNobuhiro Iwamatsu i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 1641251e490SNobuhiro Iwamatsu } 165*0bf51cb0SNobuhiro Iwamatsu 166*0bf51cb0SNobuhiro Iwamatsu static const struct sh_serial_platdata serial_platdata = { 167*0bf51cb0SNobuhiro Iwamatsu .base = SCIF0_BASE, 168*0bf51cb0SNobuhiro Iwamatsu .type = PORT_SCIF, 169*0bf51cb0SNobuhiro Iwamatsu .clk = 14745600, 170*0bf51cb0SNobuhiro Iwamatsu .clk_mode = EXT_CLK, 171*0bf51cb0SNobuhiro Iwamatsu }; 172*0bf51cb0SNobuhiro Iwamatsu 173*0bf51cb0SNobuhiro Iwamatsu U_BOOT_DEVICE(koelsch_serials) = { 174*0bf51cb0SNobuhiro Iwamatsu .name = "serial_sh", 175*0bf51cb0SNobuhiro Iwamatsu .platdata = &serial_platdata, 176*0bf51cb0SNobuhiro Iwamatsu }; 177