1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * board/renesas/gose/gose_spl.c 4 * 5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8 #include <common.h> 9 #include <malloc.h> 10 #include <dm/platform_data/serial_sh.h> 11 #include <asm/processor.h> 12 #include <asm/mach-types.h> 13 #include <asm/io.h> 14 #include <linux/errno.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/rmobile.h> 18 #include <asm/arch/rcar-mstp.h> 19 20 #include <spl.h> 21 22 #define TMU0_MSTP125 BIT(25) 23 #define SCIF0_MSTP721 BIT(21) 24 #define QSPI_MSTP917 BIT(17) 25 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 28 29 struct reg_config { 30 u16 off; 31 u32 val; 32 }; 33 34 static void dbsc_wait(u16 reg) 35 { 36 static const u32 dbsc3_0_base = DBSC3_0_BASE; 37 38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) 39 ; 40 } 41 42 static void spl_init_sys(void) 43 { 44 u32 r0 = 0; 45 46 writel(0xa5a5a500, 0xe6020004); 47 writel(0xa5a5a500, 0xe6030004); 48 49 asm volatile( 50 /* ICIALLU - Invalidate I$ to PoU */ 51 "mcr 15, 0, %0, cr7, cr5, 0 \n" 52 /* BPIALL - Invalidate branch predictors */ 53 "mcr 15, 0, %0, cr7, cr5, 6 \n" 54 /* Set SCTLR[IZ] */ 55 "mrc 15, 0, %0, cr1, cr0, 0 \n" 56 "orr %0, #0x1800 \n" 57 "mcr 15, 0, %0, cr1, cr0, 0 \n" 58 "isb sy \n" 59 :"=r"(r0)); 60 } 61 62 static void spl_init_pfc(void) 63 { 64 static const struct reg_config pfc_with_unlock[] = { 65 { 0x0090, 0x60000000 }, 66 { 0x0094, 0x60000000 }, 67 { 0x0098, 0x00800200 }, 68 { 0x009c, 0x00000000 }, 69 { 0x0020, 0x00000000 }, 70 { 0x0024, 0x00000000 }, 71 { 0x0028, 0x000244c8 }, 72 { 0x002c, 0x00000000 }, 73 { 0x0030, 0x00002400 }, 74 { 0x0034, 0x01520000 }, 75 { 0x0038, 0x00724003 }, 76 { 0x003c, 0x00000000 }, 77 { 0x0040, 0x00000000 }, 78 { 0x0044, 0x00000000 }, 79 { 0x0048, 0x00000000 }, 80 { 0x004c, 0x00000000 }, 81 { 0x0050, 0x00000000 }, 82 { 0x0054, 0x00000000 }, 83 { 0x0058, 0x00000000 }, 84 { 0x005c, 0x00000000 }, 85 { 0x0160, 0x00000000 }, 86 { 0x0004, 0xffffffff }, 87 { 0x0008, 0x00ec3fff }, 88 { 0x000c, 0x3bc001e7 }, 89 { 0x0010, 0x5bffffff }, 90 { 0x0014, 0x1ffffffb }, 91 { 0x0018, 0x01bffff0 }, 92 { 0x001c, 0xcf7fffff }, 93 { 0x0074, 0x0381fc00 }, 94 }; 95 96 static const struct reg_config pfc_without_unlock[] = { 97 { 0x0100, 0xffffffdf }, 98 { 0x0104, 0xc883c3ff }, 99 { 0x0108, 0x1201f3c9 }, 100 { 0x010c, 0x00000000 }, 101 { 0x0110, 0xffffeb04 }, 102 { 0x0114, 0xc003ffff }, 103 { 0x0118, 0x0800000f }, 104 { 0x011c, 0x001800f0 }, 105 }; 106 107 static const u32 pfc_base = 0xe6060000; 108 109 unsigned int i; 110 111 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { 112 writel(~pfc_with_unlock[i].val, pfc_base); 113 writel(pfc_with_unlock[i].val, 114 pfc_base | pfc_with_unlock[i].off); 115 } 116 117 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) 118 writel(pfc_without_unlock[i].val, 119 pfc_base | pfc_without_unlock[i].off); 120 } 121 122 static void spl_init_gpio(void) 123 { 124 static const u16 gpio_offs[] = { 125 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 126 }; 127 128 static const struct reg_config gpio_set[] = { 129 { 0x2000, 0x04381000 }, 130 { 0x5000, 0x00000000 }, 131 { 0x5800, 0x000e0000 }, 132 }; 133 134 static const struct reg_config gpio_clr[] = { 135 { 0x1000, 0x00000000 }, 136 { 0x2000, 0x04381010 }, 137 { 0x3000, 0x00000000 }, 138 { 0x4000, 0x00000000 }, 139 { 0x5000, 0x00400000 }, 140 { 0x5400, 0x00000000 }, 141 { 0x5800, 0x000e0380 }, 142 }; 143 144 static const u32 gpio_base = 0xe6050000; 145 146 unsigned int i; 147 148 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 149 writel(0, gpio_base | 0x20 | gpio_offs[i]); 150 151 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 152 writel(0, gpio_base | 0x00 | gpio_offs[i]); 153 154 for (i = 0; i < ARRAY_SIZE(gpio_set); i++) 155 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); 156 157 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) 158 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); 159 } 160 161 static void spl_init_lbsc(void) 162 { 163 static const struct reg_config lbsc_config[] = { 164 { 0x00, 0x00000020 }, 165 { 0x08, 0x00002020 }, 166 { 0x30, 0x2a103320 }, 167 { 0x38, 0xff70ff70 }, 168 }; 169 170 static const u16 lbsc_offs[] = { 171 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 172 }; 173 174 static const u32 lbsc_base = 0xfec00200; 175 176 unsigned int i; 177 178 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { 179 writel(lbsc_config[i].val, 180 lbsc_base | lbsc_config[i].off); 181 writel(lbsc_config[i].val, 182 lbsc_base | (lbsc_config[i].off + 4)); 183 } 184 185 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) 186 writel(0, lbsc_base | lbsc_offs[i]); 187 } 188 189 static void spl_init_dbsc(void) 190 { 191 static const struct reg_config dbsc_config1[] = { 192 { 0x0280, 0x0000a55a }, 193 { 0x0018, 0x21000000 }, 194 { 0x0018, 0x11000000 }, 195 { 0x0018, 0x10000000 }, 196 { 0x0290, 0x00000001 }, 197 { 0x02a0, 0x80000000 }, 198 { 0x0290, 0x00000004 }, 199 }; 200 201 static const struct reg_config dbsc_config2[] = { 202 { 0x0290, 0x00000006 }, 203 { 0x02a0, 0x0001c000 }, 204 }; 205 206 static const struct reg_config dbsc_config4[] = { 207 { 0x0290, 0x00000010 }, 208 { 0x02a0, 0xf00464db }, 209 { 0x0290, 0x00000061 }, 210 { 0x02a0, 0x0000006d }, 211 { 0x0290, 0x00000001 }, 212 { 0x02a0, 0x00000073 }, 213 { 0x0020, 0x00000007 }, 214 { 0x0024, 0x0f030a02 }, 215 { 0x0030, 0x00000001 }, 216 { 0x00b0, 0x00000000 }, 217 { 0x0040, 0x0000000b }, 218 { 0x0044, 0x00000008 }, 219 { 0x0048, 0x00000000 }, 220 { 0x0050, 0x0000000b }, 221 { 0x0054, 0x000c000b }, 222 { 0x0058, 0x00000027 }, 223 { 0x005c, 0x0000001c }, 224 { 0x0060, 0x00000006 }, 225 { 0x0064, 0x00000020 }, 226 { 0x0068, 0x00000008 }, 227 { 0x006c, 0x0000000c }, 228 { 0x0070, 0x00000009 }, 229 { 0x0074, 0x00000012 }, 230 { 0x0078, 0x000000d0 }, 231 { 0x007c, 0x00140005 }, 232 { 0x0080, 0x00050004 }, 233 { 0x0084, 0x70233005 }, 234 { 0x0088, 0x000c0000 }, 235 { 0x008c, 0x00000200 }, 236 { 0x0090, 0x00000040 }, 237 { 0x0100, 0x00000001 }, 238 { 0x00c0, 0x00020001 }, 239 { 0x00c8, 0x20042004 }, 240 { 0x0380, 0x00020002 }, 241 { 0x0390, 0x0000001f }, 242 }; 243 244 static const struct reg_config dbsc_config5[] = { 245 { 0x0244, 0x00000011 }, 246 { 0x0290, 0x00000003 }, 247 { 0x02a0, 0x0300c561 }, 248 { 0x0290, 0x00000023 }, 249 { 0x02a0, 0x00fcdb60 }, 250 { 0x0290, 0x00000011 }, 251 { 0x02a0, 0x1000040b }, 252 { 0x0290, 0x00000012 }, 253 { 0x02a0, 0x9d9cbb66 }, 254 { 0x0290, 0x00000013 }, 255 { 0x02a0, 0x1a868400 }, 256 { 0x0290, 0x00000014 }, 257 { 0x02a0, 0x300214d8 }, 258 { 0x0290, 0x00000015 }, 259 { 0x02a0, 0x00000d70 }, 260 { 0x0290, 0x00000016 }, 261 { 0x02a0, 0x00000006 }, 262 { 0x0290, 0x00000017 }, 263 { 0x02a0, 0x00000018 }, 264 { 0x0290, 0x0000001a }, 265 { 0x02a0, 0x910035c7 }, 266 { 0x0290, 0x00000004 }, 267 }; 268 269 static const struct reg_config dbsc_config6[] = { 270 { 0x0290, 0x00000001 }, 271 { 0x02a0, 0x00000181 }, 272 { 0x0018, 0x11000000 }, 273 { 0x0290, 0x00000004 }, 274 }; 275 276 static const struct reg_config dbsc_config7[] = { 277 { 0x0290, 0x00000001 }, 278 { 0x02a0, 0x0000fe01 }, 279 { 0x0304, 0x00000000 }, 280 { 0x00f4, 0x01004c20 }, 281 { 0x00f8, 0x014000aa }, 282 { 0x00e0, 0x00000140 }, 283 { 0x00e4, 0x00081860 }, 284 { 0x00e8, 0x00010000 }, 285 { 0x0290, 0x00000004 }, 286 }; 287 288 static const struct reg_config dbsc_config8[] = { 289 { 0x0014, 0x00000001 }, 290 { 0x0010, 0x00000001 }, 291 { 0x0280, 0x00000000 }, 292 }; 293 294 static const u32 dbsc3_0_base = DBSC3_0_BASE; 295 unsigned int i; 296 297 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) 298 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); 299 300 dbsc_wait(0x2a0); 301 302 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) 303 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); 304 305 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) 306 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); 307 308 dbsc_wait(0x240); 309 310 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) 311 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); 312 313 dbsc_wait(0x2a0); 314 315 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) 316 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); 317 318 dbsc_wait(0x2a0); 319 320 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) 321 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); 322 323 dbsc_wait(0x2a0); 324 325 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) 326 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); 327 328 } 329 330 static void spl_init_qspi(void) 331 { 332 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); 333 334 static const u32 qspi_base = 0xe6b10000; 335 336 writeb(0x08, qspi_base + 0x00); 337 writeb(0x00, qspi_base + 0x01); 338 writeb(0x06, qspi_base + 0x02); 339 writeb(0x01, qspi_base + 0x0a); 340 writeb(0x00, qspi_base + 0x0b); 341 writeb(0x00, qspi_base + 0x0c); 342 writeb(0x00, qspi_base + 0x0d); 343 writeb(0x00, qspi_base + 0x0e); 344 345 writew(0xe080, qspi_base + 0x10); 346 347 writeb(0xc0, qspi_base + 0x18); 348 writeb(0x00, qspi_base + 0x18); 349 writeb(0x00, qspi_base + 0x08); 350 writeb(0x48, qspi_base + 0x00); 351 } 352 353 void board_init_f(ulong dummy) 354 { 355 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 356 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 357 358 /* 359 * SD0 clock is set to 97.5MHz by default. 360 * Set SD2 to the 97.5MHz as well. 361 */ 362 writel(SD_97500KHZ, SD2CKCR); 363 364 spl_init_sys(); 365 spl_init_pfc(); 366 spl_init_gpio(); 367 spl_init_lbsc(); 368 spl_init_dbsc(); 369 spl_init_qspi(); 370 } 371 372 void spl_board_init(void) 373 { 374 /* UART clocks enabled and gd valid - init serial console */ 375 preloader_console_init(); 376 } 377 378 void board_boot_order(u32 *spl_boot_list) 379 { 380 const u32 jtag_magic = 0x1337c0de; 381 const u32 load_magic = 0xb33fc0de; 382 383 /* 384 * If JTAG probe sets special word at 0xe6300020, then it must 385 * put U-Boot into RAM and SPL will start it from RAM. 386 */ 387 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { 388 printf("JTAG boot detected!\n"); 389 390 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) 391 ; 392 393 spl_boot_list[0] = BOOT_DEVICE_RAM; 394 spl_boot_list[1] = BOOT_DEVICE_NONE; 395 396 return; 397 } 398 399 /* Boot from SPI NOR with YMODEM UART fallback. */ 400 spl_boot_list[0] = BOOT_DEVICE_SPI; 401 spl_boot_list[1] = BOOT_DEVICE_UART; 402 spl_boot_list[2] = BOOT_DEVICE_NONE; 403 } 404 405 void reset_cpu(ulong addr) 406 { 407 } 408