1 /* 2 * board/renesas/gose/gose.c 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <asm/processor.h> 12 #include <asm/mach-types.h> 13 #include <asm/io.h> 14 #include <asm/errno.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/rmobile.h> 18 #include <netdev.h> 19 #include <miiphy.h> 20 #include <i2c.h> 21 #include "qos.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define CLK2MHZ(clk) (clk / 1000 / 1000) 26 void s_init(void) 27 { 28 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 29 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 30 u32 stc; 31 32 /* Watchdog init */ 33 writel(0xA5A5A500, &rwdt->rwtcsra); 34 writel(0xA5A5A500, &swdt->swtcsra); 35 36 /* CPU frequency setting. Set to 1.5GHz */ 37 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 38 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 39 40 /* QoS */ 41 qos_init(); 42 } 43 44 #define MSTPSR1 0xE6150038 45 #define SMSTPCR1 0xE6150134 46 #define TMU0_MSTP125 (1 << 25) 47 48 #define MSTPSR7 0xE61501C4 49 #define SMSTPCR7 0xE615014C 50 #define SCIF0_MSTP721 (1 << 21) 51 52 #define MSTPSR8 0xE61509A0 53 #define SMSTPCR8 0xE6150990 54 #define ETHER_MSTP813 (1 << 13) 55 56 #define mstp_setbits(type, addr, saddr, set) \ 57 out_##type((saddr), in_##type(addr) | (set)) 58 #define mstp_clrbits(type, addr, saddr, clear) \ 59 out_##type((saddr), in_##type(addr) & ~(clear)) 60 #define mstp_setbits_le32(addr, saddr, set) \ 61 mstp_setbits(le32, addr, saddr, set) 62 #define mstp_clrbits_le32(addr, saddr, clear) \ 63 mstp_clrbits(le32, addr, saddr, clear) 64 65 int board_early_init_f(void) 66 { 67 /* TMU0 */ 68 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 69 70 /* SCIF0 */ 71 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 72 73 /* ETHER */ 74 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 75 76 return 0; 77 } 78 79 #define TSTR0 0x04 80 #define TSTR0_STR0 0x01 81 void arch_preboot_os(void) 82 { 83 /* stop TMU0 */ 84 mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); 85 /* Disable TMU0 */ 86 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 87 } 88 89 #define PUPR5 0xE6060114 90 #define PUPR5_ETH 0x3FFC0000 91 #define PUPR5_ETH_MAGIC (1 << 27) 92 93 int board_init(void) 94 { 95 /* adress of boot parameters */ 96 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 97 98 /* Init PFC controller */ 99 r8a7793_pinmux_init(); 100 101 /* ETHER Enable */ 102 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 103 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 104 gpio_request(GPIO_FN_ETH_RXD0, NULL); 105 gpio_request(GPIO_FN_ETH_RXD1, NULL); 106 gpio_request(GPIO_FN_ETH_LINK, NULL); 107 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 108 gpio_request(GPIO_FN_ETH_MDIO, NULL); 109 gpio_request(GPIO_FN_ETH_TXD1, NULL); 110 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 111 gpio_request(GPIO_FN_ETH_TXD0, NULL); 112 gpio_request(GPIO_FN_ETH_MDC, NULL); 113 gpio_request(GPIO_FN_IRQ0, NULL); 114 115 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 116 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 117 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 118 119 gpio_direction_output(GPIO_GP_5_22, 0); 120 mdelay(20); 121 gpio_set_value(GPIO_GP_5_22, 1); 122 udelay(1); 123 124 return 0; 125 } 126 127 #define CXR24 0xEE7003C0 /* MAC address high register */ 128 #define CXR25 0xEE7003C8 /* MAC address low register */ 129 130 int board_eth_init(bd_t *bis) 131 { 132 int ret = -ENODEV; 133 u32 val; 134 unsigned char enetaddr[6]; 135 136 #ifdef CONFIG_SH_ETHER 137 ret = sh_eth_initialize(bis); 138 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 139 return ret; 140 141 /* Set Mac address */ 142 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 143 enetaddr[2] << 8 | enetaddr[3]; 144 writel(val, CXR24); 145 146 val = enetaddr[4] << 8 | enetaddr[5]; 147 writel(val, CXR25); 148 #endif 149 150 return ret; 151 } 152 153 int dram_init(void) 154 { 155 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 156 157 return 0; 158 } 159 160 const struct rmobile_sysinfo sysinfo = { 161 CONFIG_RMOBILE_BOARD_STRING 162 }; 163 164 void reset_cpu(ulong addr) 165 { 166 u8 val; 167 168 i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 169 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 170 val |= 0x02; 171 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 172 } 173