1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * board/renesas/draak/draak.c 4 * This file is Draak board support. 5 * 6 * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <netdev.h> 12 #include <dm.h> 13 #include <dm/platform_data/serial_sh.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <linux/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/rmobile.h> 22 #include <asm/arch/rcar-mstp.h> 23 #include <asm/arch/sh_sdhi.h> 24 #include <i2c.h> 25 #include <mmc.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 void s_init(void) 30 { 31 } 32 33 #define GSX_MSTP112 BIT(12) /* 3DG */ 34 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ 35 #define DVFS_MSTP926 BIT(26) 36 #define HSUSB_MSTP704 BIT(4) /* HSUSB */ 37 38 int board_early_init_f(void) 39 { 40 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) 41 /* DVFS for reset */ 42 mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); 43 #endif 44 return 0; 45 } 46 47 /* HSUSB block registers */ 48 #define HSUSB_REG_LPSTS 0xE6590102 49 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) 50 #define HSUSB_REG_UGCTRL2 0xE6590184 51 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30 52 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 53 54 int board_init(void) 55 { 56 /* adress of boot parameters */ 57 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; 58 59 /* USB1 pull-up */ 60 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); 61 62 /* Configure the HSUSB block */ 63 mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); 64 /* Choice USB0SEL */ 65 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, 66 HSUSB_REG_UGCTRL2_USB0SEL_EHCI); 67 /* low power status */ 68 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); 69 70 return 0; 71 } 72 73 int dram_init(void) 74 { 75 if (fdtdec_setup_mem_size_base() != 0) 76 return -EINVAL; 77 78 return 0; 79 } 80 81 int dram_init_banksize(void) 82 { 83 fdtdec_setup_memory_banksize(); 84 85 return 0; 86 } 87 88 #define RST_BASE 0xE6160000 89 #define RST_CA57RESCNT (RST_BASE + 0x40) 90 #define RST_CA53RESCNT (RST_BASE + 0x44) 91 #define RST_RSTOUTCR (RST_BASE + 0x58) 92 #define RST_CA57_CODE 0xA5A5000F 93 #define RST_CA53_CODE 0x5A5A000F 94 95 void reset_cpu(ulong addr) 96 { 97 unsigned long midr, cputype; 98 99 asm volatile("mrs %0, midr_el1" : "=r" (midr)); 100 cputype = (midr >> 4) & 0xfff; 101 102 if (cputype == 0xd03) 103 writel(RST_CA53_CODE, RST_CA53RESCNT); 104 else if (cputype == 0xd07) 105 writel(RST_CA57_CODE, RST_CA57RESCNT); 106 else 107 hang(); 108 } 109