1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * board/renesas/draak/draak.c 4 * This file is Draak board support. 5 * 6 * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <netdev.h> 12 #include <dm.h> 13 #include <dm/platform_data/serial_sh.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <linux/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/rmobile.h> 22 #include <asm/arch/rcar-mstp.h> 23 #include <asm/arch/sh_sdhi.h> 24 #include <i2c.h> 25 #include <mmc.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 void s_init(void) 30 { 31 } 32 33 #define GSX_MSTP112 BIT(12) /* 3DG */ 34 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ 35 #define DVFS_MSTP926 BIT(26) 36 #define HSUSB_MSTP704 BIT(4) /* HSUSB */ 37 38 int board_early_init_f(void) 39 { 40 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) 41 /* DVFS for reset */ 42 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); 43 #endif 44 return 0; 45 } 46 47 /* SYSC */ 48 /* R/- 32 Power status register 2(3DG) */ 49 #define SYSC_PWRSR2 0xE6180100 50 /* -/W 32 Power resume control register 2 (3DG) */ 51 #define SYSC_PWRONCR2 0xE618010C 52 53 /* HSUSB block registers */ 54 #define HSUSB_REG_LPSTS 0xE6590102 55 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) 56 #define HSUSB_REG_UGCTRL2 0xE6590184 57 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30 58 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 59 60 int board_init(void) 61 { 62 /* adress of boot parameters */ 63 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; 64 65 /* USB1 pull-up */ 66 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); 67 68 /* Configure the HSUSB block */ 69 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); 70 /* Choice USB0SEL */ 71 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, 72 HSUSB_REG_UGCTRL2_USB0SEL_EHCI); 73 /* low power status */ 74 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); 75 76 return 0; 77 } 78 79 int dram_init(void) 80 { 81 if (fdtdec_setup_mem_size_base() != 0) 82 return -EINVAL; 83 84 return 0; 85 } 86 87 int dram_init_banksize(void) 88 { 89 fdtdec_setup_memory_banksize(); 90 91 return 0; 92 } 93 94 #define RST_BASE 0xE6160000 95 #define RST_CA57RESCNT (RST_BASE + 0x40) 96 #define RST_CA53RESCNT (RST_BASE + 0x44) 97 #define RST_RSTOUTCR (RST_BASE + 0x58) 98 #define RST_CA57_CODE 0xA5A5000F 99 #define RST_CA53_CODE 0x5A5A000F 100 101 void reset_cpu(ulong addr) 102 { 103 unsigned long midr, cputype; 104 105 asm volatile("mrs %0, midr_el1" : "=r" (midr)); 106 cputype = (midr >> 4) & 0xfff; 107 108 if (cputype == 0xd03) 109 writel(RST_CA53_CODE, RST_CA53RESCNT); 110 else if (cputype == 0xd07) 111 writel(RST_CA57_CODE, RST_CA57RESCNT); 112 else 113 hang(); 114 } 115