1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 26f107e4cSmasakazu.mochizuki.wd@hitachi.com /* 36f107e4cSmasakazu.mochizuki.wd@hitachi.com * board/renesas/blanche/blanche.c 46f107e4cSmasakazu.mochizuki.wd@hitachi.com * This file is blanche board support. 56f107e4cSmasakazu.mochizuki.wd@hitachi.com * 66f107e4cSmasakazu.mochizuki.wd@hitachi.com * Copyright (C) 2016 Renesas Electronics Corporation 76f107e4cSmasakazu.mochizuki.wd@hitachi.com */ 86f107e4cSmasakazu.mochizuki.wd@hitachi.com 96f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <common.h> 106f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <malloc.h> 116f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <netdev.h> 126f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <dm.h> 136f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <dm/platform_data/serial_sh.h> 149925f1dbSAlex Kiernan #include <environment.h> 156f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/processor.h> 166f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/mach-types.h> 176f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/io.h> 181221ce45SMasahiro Yamada #include <linux/errno.h> 196f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/arch/sys_proto.h> 206f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/gpio.h> 216f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/arch/rmobile.h> 226f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/arch/rcar-mstp.h> 236f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/arch/mmc.h> 246f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <asm/arch/sh_sdhi.h> 256f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <miiphy.h> 266f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <i2c.h> 276f107e4cSmasakazu.mochizuki.wd@hitachi.com #include <mmc.h> 286f107e4cSmasakazu.mochizuki.wd@hitachi.com #include "qos.h" 296f107e4cSmasakazu.mochizuki.wd@hitachi.com 306f107e4cSmasakazu.mochizuki.wd@hitachi.com DECLARE_GLOBAL_DATA_PTR; 316f107e4cSmasakazu.mochizuki.wd@hitachi.com 326f107e4cSmasakazu.mochizuki.wd@hitachi.com struct pin_db { 336f107e4cSmasakazu.mochizuki.wd@hitachi.com u32 addr; /* register address */ 346f107e4cSmasakazu.mochizuki.wd@hitachi.com u32 mask; /* mask value */ 356f107e4cSmasakazu.mochizuki.wd@hitachi.com u32 val; /* setting value */ 366f107e4cSmasakazu.mochizuki.wd@hitachi.com }; 376f107e4cSmasakazu.mochizuki.wd@hitachi.com 386f107e4cSmasakazu.mochizuki.wd@hitachi.com #define PMMR 0xE6060000 39d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR0 0xE6060004 40d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR1 0xE6060008 41d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR4 0xE6060014 42d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR5 0xE6060018 43d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR6 0xE606001C 44d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR7 0xE6060020 45d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR8 0xE6060024 46d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR9 0xE6060028 476f107e4cSmasakazu.mochizuki.wd@hitachi.com #define GPSR10 0xE606002C 48d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define GPSR11 0xE6060030 49d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define IPSR6 0xE6060058 50d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define PUPR2 0xE6060108 516f107e4cSmasakazu.mochizuki.wd@hitachi.com #define PUPR3 0xE606010C 52d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define PUPR4 0xE6060110 53d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define PUPR5 0xE6060114 54d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define PUPR7 0xE606011C 55d8fc402aSmasakazu.mochizuki.wd@hitachi.com #define PUPR9 0xE6060124 566f107e4cSmasakazu.mochizuki.wd@hitachi.com #define PUPR10 0xE6060128 576f107e4cSmasakazu.mochizuki.wd@hitachi.com #define PUPR11 0xE606012C 586f107e4cSmasakazu.mochizuki.wd@hitachi.com 596f107e4cSmasakazu.mochizuki.wd@hitachi.com #define CPG_PLL1CR 0xE6150028 606f107e4cSmasakazu.mochizuki.wd@hitachi.com #define CPG_PLL3CR 0xE61500DC 616f107e4cSmasakazu.mochizuki.wd@hitachi.com 626f107e4cSmasakazu.mochizuki.wd@hitachi.com #define SetREG(x) \ 636f107e4cSmasakazu.mochizuki.wd@hitachi.com writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr) 646f107e4cSmasakazu.mochizuki.wd@hitachi.com 656f107e4cSmasakazu.mochizuki.wd@hitachi.com #define SetGuardREG(x) \ 666f107e4cSmasakazu.mochizuki.wd@hitachi.com { \ 676f107e4cSmasakazu.mochizuki.wd@hitachi.com u32 val; \ 686f107e4cSmasakazu.mochizuki.wd@hitachi.com val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \ 696f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(~val, PMMR); \ 706f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(val, (x)->addr); \ 716f107e4cSmasakazu.mochizuki.wd@hitachi.com } 726f107e4cSmasakazu.mochizuki.wd@hitachi.com 736f107e4cSmasakazu.mochizuki.wd@hitachi.com struct pin_db pin_guard[] = { 74d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR0, 0xFFFFFFFF, 0x0BFFFFFF }, 75d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR1, 0xFFFFFFFF, 0x002FFFFF }, 76d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR4, 0xFFFFFFFF, 0x00000FFF }, 77d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR5, 0xFFFFFFFF, 0x00010FFF }, 78d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR6, 0xFFFFFFFF, 0x00010FFF }, 79d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR7, 0xFFFFFFFF, 0x00010FFF }, 80d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR8, 0xFFFFFFFF, 0x00010FFF }, 81d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR9, 0xFFFFFFFF, 0x00010FFF }, 826f107e4cSmasakazu.mochizuki.wd@hitachi.com { GPSR10, 0xFFFFFFFF, 0x04006000 }, 83d8fc402aSmasakazu.mochizuki.wd@hitachi.com { GPSR11, 0xFFFFFFFF, 0x303FEFE0 }, 84d8fc402aSmasakazu.mochizuki.wd@hitachi.com { IPSR6, 0xFFFFFFFF, 0x0002000E }, 856f107e4cSmasakazu.mochizuki.wd@hitachi.com }; 866f107e4cSmasakazu.mochizuki.wd@hitachi.com 876f107e4cSmasakazu.mochizuki.wd@hitachi.com struct pin_db pin_tbl[] = { 88d8fc402aSmasakazu.mochizuki.wd@hitachi.com { PUPR2, 0xFFFFFFFF, 0x00000000 }, 896f107e4cSmasakazu.mochizuki.wd@hitachi.com { PUPR3, 0xFFFFFFFF, 0x0803FF40 }, 90d8fc402aSmasakazu.mochizuki.wd@hitachi.com { PUPR4, 0xFFFFFFFF, 0x0000FFFF }, 91d8fc402aSmasakazu.mochizuki.wd@hitachi.com { PUPR5, 0xFFFFFFFF, 0x00010FFF }, 92d8fc402aSmasakazu.mochizuki.wd@hitachi.com { PUPR7, 0xFFFFFFFF, 0x0001AFFF }, 93d8fc402aSmasakazu.mochizuki.wd@hitachi.com { PUPR9, 0xFFFFFFFF, 0x0001CFFF }, 946f107e4cSmasakazu.mochizuki.wd@hitachi.com { PUPR10, 0xFFFFFFFF, 0xC0438001 }, 956f107e4cSmasakazu.mochizuki.wd@hitachi.com { PUPR11, 0xFFFFFFFF, 0x0FC00007 }, 966f107e4cSmasakazu.mochizuki.wd@hitachi.com }; 976f107e4cSmasakazu.mochizuki.wd@hitachi.com 986f107e4cSmasakazu.mochizuki.wd@hitachi.com void pin_init(void) 996f107e4cSmasakazu.mochizuki.wd@hitachi.com { 1006f107e4cSmasakazu.mochizuki.wd@hitachi.com struct pin_db *db; 1016f107e4cSmasakazu.mochizuki.wd@hitachi.com 1026f107e4cSmasakazu.mochizuki.wd@hitachi.com for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) { 1036f107e4cSmasakazu.mochizuki.wd@hitachi.com SetGuardREG(db); 1046f107e4cSmasakazu.mochizuki.wd@hitachi.com } 1056f107e4cSmasakazu.mochizuki.wd@hitachi.com for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) { 1066f107e4cSmasakazu.mochizuki.wd@hitachi.com SetREG(db); 1076f107e4cSmasakazu.mochizuki.wd@hitachi.com } 1086f107e4cSmasakazu.mochizuki.wd@hitachi.com } 1096f107e4cSmasakazu.mochizuki.wd@hitachi.com 1106f107e4cSmasakazu.mochizuki.wd@hitachi.com #define s_init_wait(cnt) \ 1116f107e4cSmasakazu.mochizuki.wd@hitachi.com ({ \ 1126f107e4cSmasakazu.mochizuki.wd@hitachi.com volatile u32 i = 0x10000 * cnt; \ 1136f107e4cSmasakazu.mochizuki.wd@hitachi.com while (i > 0) \ 1146f107e4cSmasakazu.mochizuki.wd@hitachi.com i--; \ 1156f107e4cSmasakazu.mochizuki.wd@hitachi.com }) 1166f107e4cSmasakazu.mochizuki.wd@hitachi.com 1176f107e4cSmasakazu.mochizuki.wd@hitachi.com void s_init(void) 1186f107e4cSmasakazu.mochizuki.wd@hitachi.com { 1196f107e4cSmasakazu.mochizuki.wd@hitachi.com struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 1206f107e4cSmasakazu.mochizuki.wd@hitachi.com struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 1216f107e4cSmasakazu.mochizuki.wd@hitachi.com u32 cpu_type; 1226f107e4cSmasakazu.mochizuki.wd@hitachi.com 1236f107e4cSmasakazu.mochizuki.wd@hitachi.com cpu_type = rmobile_get_cpu_type(); 1246f107e4cSmasakazu.mochizuki.wd@hitachi.com if (cpu_type == 0x4A) { 1256f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x4D000000, CPG_PLL1CR); 1266f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x4F000000, CPG_PLL3CR); 1276f107e4cSmasakazu.mochizuki.wd@hitachi.com } 1286f107e4cSmasakazu.mochizuki.wd@hitachi.com 1296f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Watchdog init */ 1306f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0xA5A5A500, &rwdt->rwtcsra); 1316f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0xA5A5A500, &swdt->swtcsra); 1326f107e4cSmasakazu.mochizuki.wd@hitachi.com 1336f107e4cSmasakazu.mochizuki.wd@hitachi.com /* QoS(Quality-of-Service) Init */ 1346f107e4cSmasakazu.mochizuki.wd@hitachi.com qos_init(); 1356f107e4cSmasakazu.mochizuki.wd@hitachi.com 1366f107e4cSmasakazu.mochizuki.wd@hitachi.com /* SCIF Init */ 1376f107e4cSmasakazu.mochizuki.wd@hitachi.com pin_init(); 1386f107e4cSmasakazu.mochizuki.wd@hitachi.com 139e856bdcfSMasahiro Yamada #if defined(CONFIG_MTD_NOR_FLASH) 1406f107e4cSmasakazu.mochizuki.wd@hitachi.com struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE; 1416f107e4cSmasakazu.mochizuki.wd@hitachi.com struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE; 1426f107e4cSmasakazu.mochizuki.wd@hitachi.com 1436f107e4cSmasakazu.mochizuki.wd@hitachi.com /* LBSC */ 1446f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000020, &lbsc->cs0ctrl); 1456f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000020, &lbsc->cs1ctrl); 1466f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00002020, &lbsc->ecs0ctrl); 1476f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00002020, &lbsc->ecs1ctrl); 1486f107e4cSmasakazu.mochizuki.wd@hitachi.com 1496f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x2A103320, &lbsc->cswcr0); 1506f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x2A103320, &lbsc->cswcr1); 1516f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x19102110, &lbsc->ecswcr0); 1526f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x19102110, &lbsc->ecswcr1); 1536f107e4cSmasakazu.mochizuki.wd@hitachi.com 1546f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DBSC3 */ 1556f107e4cSmasakazu.mochizuki.wd@hitachi.com s_init_wait(10); 1566f107e4cSmasakazu.mochizuki.wd@hitachi.com 1576f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000A55A, &dbsc3_0->dbpdlck); 1586f107e4cSmasakazu.mochizuki.wd@hitachi.com 1596f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */ 1606f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */ 1616f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */ 1626f107e4cSmasakazu.mochizuki.wd@hitachi.com 1636f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Stop Auto-Calibration */ 1646f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000001, &dbsc3_0->dbpdrga); 1656f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x80000000, &dbsc3_0->dbpdrgd); 1666f107e4cSmasakazu.mochizuki.wd@hitachi.com 1676f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000004, &dbsc3_0->dbpdrga); 1686f107e4cSmasakazu.mochizuki.wd@hitachi.com while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001); 1696f107e4cSmasakazu.mochizuki.wd@hitachi.com 1706f107e4cSmasakazu.mochizuki.wd@hitachi.com /* PLLCR: PLL Control Register */ 1716f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000006, &dbsc3_0->dbpdrga); 1726f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440 1736f107e4cSmasakazu.mochizuki.wd@hitachi.com 1746f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DXCCR: DATX8 Common Configuration Register */ 1756f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000000F, &dbsc3_0->dbpdrga); 1766f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00181EE4, &dbsc3_0->dbpdrgd); 1776f107e4cSmasakazu.mochizuki.wd@hitachi.com 1786f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DSGCR :DDR System General Configuration Register */ 1796f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000010, &dbsc3_0->dbpdrga); 1806f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0xF00464DB, &dbsc3_0->dbpdrgd); 1816f107e4cSmasakazu.mochizuki.wd@hitachi.com 1826f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000061, &dbsc3_0->dbpdrga); 1836f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000008D, &dbsc3_0->dbpdrgd); 1846f107e4cSmasakazu.mochizuki.wd@hitachi.com 1856f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Re-Execute ZQ calibration */ 1866f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000001, &dbsc3_0->dbpdrga); 1876f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000073, &dbsc3_0->dbpdrgd); 1886f107e4cSmasakazu.mochizuki.wd@hitachi.com 1896f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000007, &dbsc3_0->dbkind); 1906f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0F030A02, &dbsc3_0->dbconf0); 1916f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000001, &dbsc3_0->dbphytype); 1926f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000000, &dbsc3_0->dbbl); 1936f107e4cSmasakazu.mochizuki.wd@hitachi.com 1946f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11 1956f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8 1966f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0 1976f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11 1986f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11 1996f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39 2006f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28 2016f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6 2026f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32 2036f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8 2046f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12 2056f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9 2066f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18 2076f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208 2086f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00140005, &dbsc3_0->dbtr14); 2096f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00050004, &dbsc3_0->dbtr15); 2106f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */ 2116f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x000C0000, &dbsc3_0->dbtr17); 2126f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000300, &dbsc3_0->dbtr18); 2136f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000040, &dbsc3_0->dbtr19); 2146f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000001, &dbsc3_0->dbrnk0); 2156f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00020001, &dbsc3_0->dbadj0); 2166f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */ 2176f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */ 2186f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000001F, &dbsc3_0->dbwt0cnf4); 2196f107e4cSmasakazu.mochizuki.wd@hitachi.com 2206f107e4cSmasakazu.mochizuki.wd@hitachi.com while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001); 2216f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000011, &dbsc3_0->dbdficnt); 2226f107e4cSmasakazu.mochizuki.wd@hitachi.com 2236f107e4cSmasakazu.mochizuki.wd@hitachi.com /* PGCR1 :PHY General Configuration Register 1 */ 2246f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000003, &dbsc3_0->dbpdrga); 2256f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */ 2266f107e4cSmasakazu.mochizuki.wd@hitachi.com 2276f107e4cSmasakazu.mochizuki.wd@hitachi.com /* PGCR2: PHY General Configuration Registers 2 */ 2286f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000023, &dbsc3_0->dbpdrga); 2296f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00FCDB60, &dbsc3_0->dbpdrgd); 2306f107e4cSmasakazu.mochizuki.wd@hitachi.com 2316f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000011, &dbsc3_0->dbpdrga); 2326f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x1000040B, &dbsc3_0->dbpdrgd); 2336f107e4cSmasakazu.mochizuki.wd@hitachi.com 2346f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DTPR0 :DRAM Timing Parameters Register 0 */ 2356f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000012, &dbsc3_0->dbpdrga); 2366f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x9D9CBB66, &dbsc3_0->dbpdrgd); 2376f107e4cSmasakazu.mochizuki.wd@hitachi.com 2386f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DTPR1 :DRAM Timing Parameters Register 1 */ 2396f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000013, &dbsc3_0->dbpdrga); 2406f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x1A868400, &dbsc3_0->dbpdrgd); 2416f107e4cSmasakazu.mochizuki.wd@hitachi.com 2426f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DTPR2 ::DRAM Timing Parameters Register 2 */ 2436f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000014, &dbsc3_0->dbpdrga); 2446f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x300214D8, &dbsc3_0->dbpdrgd); 2456f107e4cSmasakazu.mochizuki.wd@hitachi.com 2466f107e4cSmasakazu.mochizuki.wd@hitachi.com /* MR0 :Mode Register 0 */ 2476f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000015, &dbsc3_0->dbpdrga); 2486f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000D70, &dbsc3_0->dbpdrgd); 2496f107e4cSmasakazu.mochizuki.wd@hitachi.com 2506f107e4cSmasakazu.mochizuki.wd@hitachi.com /* MR1 :Mode Register 1 */ 2516f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000016, &dbsc3_0->dbpdrga); 2526f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */ 2536f107e4cSmasakazu.mochizuki.wd@hitachi.com 2546f107e4cSmasakazu.mochizuki.wd@hitachi.com /* MR2 :Mode Register 2 */ 2556f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000017, &dbsc3_0->dbpdrga); 2566f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */ 2576f107e4cSmasakazu.mochizuki.wd@hitachi.com 2586f107e4cSmasakazu.mochizuki.wd@hitachi.com /* VREF(ZQCAL) */ 2596f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000001A, &dbsc3_0->dbpdrga); 2606f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x910035C7, &dbsc3_0->dbpdrgd); 2616f107e4cSmasakazu.mochizuki.wd@hitachi.com 2626f107e4cSmasakazu.mochizuki.wd@hitachi.com /* PGSR0 :PHY General Status Registers 0 */ 2636f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000004, &dbsc3_0->dbpdrga); 2646f107e4cSmasakazu.mochizuki.wd@hitachi.com while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001); 2656f107e4cSmasakazu.mochizuki.wd@hitachi.com 2666f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DRAM Init (set MRx etc) */ 2676f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000001, &dbsc3_0->dbpdrga); 2686f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000181, &dbsc3_0->dbpdrgd); 2696f107e4cSmasakazu.mochizuki.wd@hitachi.com 2706f107e4cSmasakazu.mochizuki.wd@hitachi.com /* CKE = H */ 2716f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */ 2726f107e4cSmasakazu.mochizuki.wd@hitachi.com 2736f107e4cSmasakazu.mochizuki.wd@hitachi.com /* PGSR0 :PHY General Status Registers 0 */ 2746f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000004, &dbsc3_0->dbpdrga); 2756f107e4cSmasakazu.mochizuki.wd@hitachi.com while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001); 2766f107e4cSmasakazu.mochizuki.wd@hitachi.com 2776f107e4cSmasakazu.mochizuki.wd@hitachi.com /* RAM ACC Training */ 2786f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000001, &dbsc3_0->dbpdrga); 2796f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x0000FE01, &dbsc3_0->dbpdrgd); 2806f107e4cSmasakazu.mochizuki.wd@hitachi.com 2816f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Bus control 0 */ 2826f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000000, &dbsc3_0->dbbs0cnt1); 2836f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DDR3 Calibration set */ 2846f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x01004C20, &dbsc3_0->dbcalcnf); 2856f107e4cSmasakazu.mochizuki.wd@hitachi.com /* DDR3 Calibration timing */ 2866f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x014000AA, &dbsc3_0->dbcaltr); 2876f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Refresh */ 2886f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000140, &dbsc3_0->dbrfcnf0); 2896f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00081860, &dbsc3_0->dbrfcnf1); 2906f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00010000, &dbsc3_0->dbrfcnf2); 2916f107e4cSmasakazu.mochizuki.wd@hitachi.com 2926f107e4cSmasakazu.mochizuki.wd@hitachi.com /* PGSR0 :PHY General Status Registers 0 */ 2936f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000004, &dbsc3_0->dbpdrga); 2946f107e4cSmasakazu.mochizuki.wd@hitachi.com while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001); 2956f107e4cSmasakazu.mochizuki.wd@hitachi.com 2966f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Enable Auto-Refresh */ 2976f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000001, &dbsc3_0->dbrfen); 2986f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Permit DDR-Access */ 2996f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000001, &dbsc3_0->dbacen); 3006f107e4cSmasakazu.mochizuki.wd@hitachi.com 3016f107e4cSmasakazu.mochizuki.wd@hitachi.com /* This locks the access to the PHY unit registers */ 3026f107e4cSmasakazu.mochizuki.wd@hitachi.com writel(0x00000000, &dbsc3_0->dbpdlck); 303e856bdcfSMasahiro Yamada #endif /* CONFIG_MTD_NOR_FLASH */ 3046f107e4cSmasakazu.mochizuki.wd@hitachi.com 3056f107e4cSmasakazu.mochizuki.wd@hitachi.com } 3066f107e4cSmasakazu.mochizuki.wd@hitachi.com 3076f107e4cSmasakazu.mochizuki.wd@hitachi.com #define TMU0_MSTP125 (1 << 25) 3086f107e4cSmasakazu.mochizuki.wd@hitachi.com #define SCIF0_MSTP721 (1 << 21) 3096f107e4cSmasakazu.mochizuki.wd@hitachi.com #define SDHI0_MSTP314 (1 << 14) 3106f107e4cSmasakazu.mochizuki.wd@hitachi.com #define QSPI_MSTP917 (1 << 17) 3116f107e4cSmasakazu.mochizuki.wd@hitachi.com 3126f107e4cSmasakazu.mochizuki.wd@hitachi.com int board_early_init_f(void) 3136f107e4cSmasakazu.mochizuki.wd@hitachi.com { 3146f107e4cSmasakazu.mochizuki.wd@hitachi.com /* TMU0 */ 3156f107e4cSmasakazu.mochizuki.wd@hitachi.com mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 3166f107e4cSmasakazu.mochizuki.wd@hitachi.com /* SCIF0 */ 3176f107e4cSmasakazu.mochizuki.wd@hitachi.com mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 3186f107e4cSmasakazu.mochizuki.wd@hitachi.com /* SDHI0 */ 3196f107e4cSmasakazu.mochizuki.wd@hitachi.com mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314); 3206f107e4cSmasakazu.mochizuki.wd@hitachi.com /* QSPI */ 3216f107e4cSmasakazu.mochizuki.wd@hitachi.com mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); 3226f107e4cSmasakazu.mochizuki.wd@hitachi.com 3236f107e4cSmasakazu.mochizuki.wd@hitachi.com return 0; 3246f107e4cSmasakazu.mochizuki.wd@hitachi.com } 3256f107e4cSmasakazu.mochizuki.wd@hitachi.com 3266f107e4cSmasakazu.mochizuki.wd@hitachi.com DECLARE_GLOBAL_DATA_PTR; 3276f107e4cSmasakazu.mochizuki.wd@hitachi.com int board_init(void) 3286f107e4cSmasakazu.mochizuki.wd@hitachi.com { 3296f107e4cSmasakazu.mochizuki.wd@hitachi.com /* adress of boot parameters */ 3306f107e4cSmasakazu.mochizuki.wd@hitachi.com gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 3316f107e4cSmasakazu.mochizuki.wd@hitachi.com 3326f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Init PFC controller */ 3336f107e4cSmasakazu.mochizuki.wd@hitachi.com r8a7792_pinmux_init(); 3346f107e4cSmasakazu.mochizuki.wd@hitachi.com 3356f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D0, NULL); 3366f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D1, NULL); 3376f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D2, NULL); 3386f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D3, NULL); 3396f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D4, NULL); 3406f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D5, NULL); 3416f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D6, NULL); 3426f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D7, NULL); 3436f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D8, NULL); 3446f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D9, NULL); 3456f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D10, NULL); 3466f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D11, NULL); 3476f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D12, NULL); 3486f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D13, NULL); 3496f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D14, NULL); 3506f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_D15, NULL); 3516f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A0, NULL); 3526f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A1, NULL); 3536f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A2, NULL); 3546f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A3, NULL); 3556f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A4, NULL); 3566f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A5, NULL); 3576f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A6, NULL); 3586f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A7, NULL); 3596f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A8, NULL); 3606f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A9, NULL); 3616f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A10, NULL); 3626f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A11, NULL); 3636f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A12, NULL); 3646f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A13, NULL); 3656f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A14, NULL); 3666f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A15, NULL); 3676f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A16, NULL); 3686f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A17, NULL); 3696f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A18, NULL); 3706f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A19, NULL); 371e856bdcfSMasahiro Yamada #if !defined(CONFIG_MTD_NOR_FLASH) 3726f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_MOSI_IO0, NULL); 3736f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_MISO_IO1, NULL); 3746f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_IO2, NULL); 3756f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_IO3, NULL); 3766f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SPCLK, NULL); 3776f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SSL, NULL); 378e856bdcfSMasahiro Yamada #else /* CONFIG_MTD_NOR_FLASH */ 3796f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A20, NULL); 3806f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A21, NULL); 3816f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A22, NULL); 3826f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A23, NULL); 3836f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A24, NULL); 3846f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_A25, NULL); 385e856bdcfSMasahiro Yamada #endif /* CONFIG_MTD_NOR_FLASH */ 3866f107e4cSmasakazu.mochizuki.wd@hitachi.com 3876f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_CS1_A26, NULL); 3886f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_EX_CS0, NULL); 3896f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_EX_CS1, NULL); 3906f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_BS, NULL); 3916f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_RD, NULL); 3926f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_WE0, NULL); 3936f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_WE1, NULL); 3946f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_EX_WAIT0, NULL); 3956f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_IRQ0, NULL); 3966f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_IRQ2, NULL); 3976f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_IRQ3, NULL); 3986f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_CS0, NULL); 3996f107e4cSmasakazu.mochizuki.wd@hitachi.com 4006f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Init timer */ 4016f107e4cSmasakazu.mochizuki.wd@hitachi.com timer_init(); 4026f107e4cSmasakazu.mochizuki.wd@hitachi.com 4036f107e4cSmasakazu.mochizuki.wd@hitachi.com return 0; 4046f107e4cSmasakazu.mochizuki.wd@hitachi.com } 4056f107e4cSmasakazu.mochizuki.wd@hitachi.com 4066f107e4cSmasakazu.mochizuki.wd@hitachi.com /* 4076f107e4cSmasakazu.mochizuki.wd@hitachi.com Added for BLANCHE(R-CarV2H board) 4086f107e4cSmasakazu.mochizuki.wd@hitachi.com */ 4096f107e4cSmasakazu.mochizuki.wd@hitachi.com int board_eth_init(bd_t *bis) 4106f107e4cSmasakazu.mochizuki.wd@hitachi.com { 4116f107e4cSmasakazu.mochizuki.wd@hitachi.com int rc = 0; 4126f107e4cSmasakazu.mochizuki.wd@hitachi.com 4136f107e4cSmasakazu.mochizuki.wd@hitachi.com #ifdef CONFIG_SMC911X 4146f107e4cSmasakazu.mochizuki.wd@hitachi.com #define STR_ENV_ETHADDR "ethaddr" 4156f107e4cSmasakazu.mochizuki.wd@hitachi.com 4166f107e4cSmasakazu.mochizuki.wd@hitachi.com struct eth_device *dev; 4176f107e4cSmasakazu.mochizuki.wd@hitachi.com uchar eth_addr[6]; 4186f107e4cSmasakazu.mochizuki.wd@hitachi.com 4196f107e4cSmasakazu.mochizuki.wd@hitachi.com rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 4206f107e4cSmasakazu.mochizuki.wd@hitachi.com 42135affd7aSSimon Glass if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) { 4226f107e4cSmasakazu.mochizuki.wd@hitachi.com dev = eth_get_dev_by_index(0); 4236f107e4cSmasakazu.mochizuki.wd@hitachi.com if (dev) { 424fd1e959eSSimon Glass eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); 4256f107e4cSmasakazu.mochizuki.wd@hitachi.com } else { 4266f107e4cSmasakazu.mochizuki.wd@hitachi.com printf("blanche: Couldn't get eth device\n"); 4276f107e4cSmasakazu.mochizuki.wd@hitachi.com rc = -1; 4286f107e4cSmasakazu.mochizuki.wd@hitachi.com } 4296f107e4cSmasakazu.mochizuki.wd@hitachi.com } 4306f107e4cSmasakazu.mochizuki.wd@hitachi.com 4316f107e4cSmasakazu.mochizuki.wd@hitachi.com #endif 4326f107e4cSmasakazu.mochizuki.wd@hitachi.com 4336f107e4cSmasakazu.mochizuki.wd@hitachi.com return rc; 4346f107e4cSmasakazu.mochizuki.wd@hitachi.com } 4356f107e4cSmasakazu.mochizuki.wd@hitachi.com 4366f107e4cSmasakazu.mochizuki.wd@hitachi.com int board_mmc_init(bd_t *bis) 4376f107e4cSmasakazu.mochizuki.wd@hitachi.com { 4386f107e4cSmasakazu.mochizuki.wd@hitachi.com int ret = -ENODEV; 4396f107e4cSmasakazu.mochizuki.wd@hitachi.com 4406f107e4cSmasakazu.mochizuki.wd@hitachi.com #ifdef CONFIG_SH_SDHI 4416f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SD0_DAT0, NULL); 4426f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SD0_DAT1, NULL); 4436f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SD0_DAT2, NULL); 4446f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SD0_DAT3, NULL); 4456f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SD0_CLK, NULL); 4466f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SD0_CMD, NULL); 4476f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_FN_SD0_CD, NULL); 4486f107e4cSmasakazu.mochizuki.wd@hitachi.com 4496f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_request(GPIO_GP_11_12, NULL); 4506f107e4cSmasakazu.mochizuki.wd@hitachi.com gpio_direction_output(GPIO_GP_11_12, 1); /* power on */ 4516f107e4cSmasakazu.mochizuki.wd@hitachi.com 4526f107e4cSmasakazu.mochizuki.wd@hitachi.com 4536f107e4cSmasakazu.mochizuki.wd@hitachi.com ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 4546f107e4cSmasakazu.mochizuki.wd@hitachi.com SH_SDHI_QUIRK_16BIT_BUF); 4556f107e4cSmasakazu.mochizuki.wd@hitachi.com 4566f107e4cSmasakazu.mochizuki.wd@hitachi.com if (ret) 4576f107e4cSmasakazu.mochizuki.wd@hitachi.com return ret; 4586f107e4cSmasakazu.mochizuki.wd@hitachi.com #endif 4596f107e4cSmasakazu.mochizuki.wd@hitachi.com return ret; 4606f107e4cSmasakazu.mochizuki.wd@hitachi.com } 4616f107e4cSmasakazu.mochizuki.wd@hitachi.com 4626f107e4cSmasakazu.mochizuki.wd@hitachi.com int dram_init(void) 4636f107e4cSmasakazu.mochizuki.wd@hitachi.com { 4646f107e4cSmasakazu.mochizuki.wd@hitachi.com gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 4656f107e4cSmasakazu.mochizuki.wd@hitachi.com gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 4666f107e4cSmasakazu.mochizuki.wd@hitachi.com 4676f107e4cSmasakazu.mochizuki.wd@hitachi.com return 0; 4686f107e4cSmasakazu.mochizuki.wd@hitachi.com } 4696f107e4cSmasakazu.mochizuki.wd@hitachi.com 4706f107e4cSmasakazu.mochizuki.wd@hitachi.com void reset_cpu(ulong addr) 4716f107e4cSmasakazu.mochizuki.wd@hitachi.com { 4726f107e4cSmasakazu.mochizuki.wd@hitachi.com } 4736f107e4cSmasakazu.mochizuki.wd@hitachi.com 4746f107e4cSmasakazu.mochizuki.wd@hitachi.com static const struct sh_serial_platdata serial_platdata = { 4756f107e4cSmasakazu.mochizuki.wd@hitachi.com .base = SCIF0_BASE, 4766f107e4cSmasakazu.mochizuki.wd@hitachi.com .type = PORT_SCIF, 4776f107e4cSmasakazu.mochizuki.wd@hitachi.com .clk = 14745600, 4786f107e4cSmasakazu.mochizuki.wd@hitachi.com .clk_mode = EXT_CLK, 4796f107e4cSmasakazu.mochizuki.wd@hitachi.com }; 4806f107e4cSmasakazu.mochizuki.wd@hitachi.com 4816f107e4cSmasakazu.mochizuki.wd@hitachi.com U_BOOT_DEVICE(blanche_serials) = { 4826f107e4cSmasakazu.mochizuki.wd@hitachi.com .name = "serial_sh", 4836f107e4cSmasakazu.mochizuki.wd@hitachi.com .platdata = &serial_platdata, 4846f107e4cSmasakazu.mochizuki.wd@hitachi.com }; 485