1 /* 2 * Copyright (C) 2008 Renesas Solutions Corp. 3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <asm/io.h> 23 #include <asm/processor.h> 24 25 /* PRI control register */ 26 #define PRPRICR5 0xFF800048 /* LMB */ 27 #define PRPRICR5_D 0x2a 28 29 /* FPGA control */ 30 #define FPGA_NAND_CTL 0xB410020C 31 #define FPGA_NAND_RST 0x0008 32 #define FPGA_NAND_INIT 0x0000 33 #define FPGA_NAND_RST_WAIT 10000 34 35 /* I/O port data */ 36 #define PACR_D 0x0000 37 #define PBCR_D 0x0000 38 #define PCCR_D 0x1000 39 #define PDCR_D 0x0000 40 #define PECR_D 0x0410 41 #define PFCR_D 0xffff 42 #define PGCR_D 0x0000 43 #define PHCR_D 0x5011 44 #define PJCR_D 0x4400 45 #define PKCR_D 0x7c00 46 #define PLCR_D 0x0000 47 #define PMCR_D 0x0000 48 #define PNCR_D 0x0000 49 #define PQCR_D 0x0000 50 #define PRCR_D 0x0000 51 #define PSCR_D 0x0000 52 #define PTCR_D 0x0010 53 #define PUCR_D 0x0fff 54 #define PVCR_D 0xffff 55 #define PWCR_D 0x0000 56 #define PXCR_D 0x7500 57 #define PYCR_D 0x0000 58 #define PZCR_D 0x5540 59 60 /* Pin Function Controler data */ 61 #define PSELA_D 0x1410 62 #define PSELB_D 0x0140 63 #define PSELC_D 0x0000 64 #define PSELD_D 0x0400 65 66 /* I/O Buffer Hi-Z data */ 67 #define HIZCRA_D 0x0000 68 #define HIZCRB_D 0x1000 69 #define HIZCRC_D 0x0000 70 #define HIZCRD_D 0x0000 71 72 /* Module select reg data */ 73 #define MSELCRA_D 0x0014 74 #define MSELCRB_D 0x0018 75 76 /* Module Stop reg Data */ 77 #define MSTPCR2_D 0xFFD9F280 78 79 /* CPLD loader */ 80 extern void init_cpld(void); 81 82 int checkboard(void) 83 { 84 puts("BOARD: AP325RXA\n"); 85 return 0; 86 } 87 88 int board_init(void) 89 { 90 /* Pin Function Controler Init */ 91 outw(PSELA_D, PSELA); 92 outw(PSELB_D, PSELB); 93 outw(PSELC_D, PSELC); 94 outw(PSELD_D, PSELD); 95 96 /* I/O Buffer Hi-Z Init */ 97 outw(HIZCRA_D, HIZCRA); 98 outw(HIZCRB_D, HIZCRB); 99 outw(HIZCRC_D, HIZCRC); 100 outw(HIZCRD_D, HIZCRD); 101 102 /* Module select reg Init */ 103 outw(MSELCRA_D, MSELCRA); 104 outw(MSELCRB_D, MSELCRB); 105 106 /* Module Stop reg Init */ 107 outl(MSTPCR2_D, MSTPCR2); 108 109 /* I/O ports */ 110 outw(PACR_D, PACR); 111 outw(PBCR_D, PBCR); 112 outw(PCCR_D, PCCR); 113 outw(PDCR_D, PDCR); 114 outw(PECR_D, PECR); 115 outw(PFCR_D, PFCR); 116 outw(PGCR_D, PGCR); 117 outw(PHCR_D, PHCR); 118 outw(PJCR_D, PJCR); 119 outw(PKCR_D, PKCR); 120 outw(PLCR_D, PLCR); 121 outw(PMCR_D, PMCR); 122 outw(PNCR_D, PNCR); 123 outw(PQCR_D, PQCR); 124 outw(PRCR_D, PRCR); 125 outw(PSCR_D, PSCR); 126 outw(PTCR_D, PTCR); 127 outw(PUCR_D, PUCR); 128 outw(PVCR_D, PVCR); 129 outw(PWCR_D, PWCR); 130 outw(PXCR_D, PXCR); 131 outw(PYCR_D, PYCR); 132 outw(PZCR_D, PZCR); 133 134 /* PRI control register Init */ 135 outl(PRPRICR5_D, PRPRICR5); 136 137 /* cpld init */ 138 init_cpld(); 139 140 return 0; 141 } 142 143 int dram_init(void) 144 { 145 DECLARE_GLOBAL_DATA_PTR; 146 147 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 148 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 149 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); 150 return 0; 151 } 152 153 void led_set_state(unsigned short value) 154 { 155 } 156 157 void ide_set_reset(int idereset) 158 { 159 outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ 160 udelay(FPGA_NAND_RST_WAIT); 161 outw(FPGA_NAND_INIT, FPGA_NAND_CTL); 162 } 163