1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2008 Renesas Solutions Corp. 4 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <asm/io.h> 10 #include <asm/processor.h> 11 12 /* PRI control register */ 13 #define PRPRICR5 0xFF800048 /* LMB */ 14 #define PRPRICR5_D 0x2a 15 16 /* FPGA control */ 17 #define FPGA_NAND_CTL 0xB410020C 18 #define FPGA_NAND_RST 0x0008 19 #define FPGA_NAND_INIT 0x0000 20 #define FPGA_NAND_RST_WAIT 10000 21 22 /* I/O port data */ 23 #define PACR_D 0x0000 24 #define PBCR_D 0x0000 25 #define PCCR_D 0x1000 26 #define PDCR_D 0x0000 27 #define PECR_D 0x0410 28 #define PFCR_D 0xffff 29 #define PGCR_D 0x0000 30 #define PHCR_D 0x5011 31 #define PJCR_D 0x4400 32 #define PKCR_D 0x7c00 33 #define PLCR_D 0x0000 34 #define PMCR_D 0x0000 35 #define PNCR_D 0x0000 36 #define PQCR_D 0x0000 37 #define PRCR_D 0x0000 38 #define PSCR_D 0x0000 39 #define PTCR_D 0x0010 40 #define PUCR_D 0x0fff 41 #define PVCR_D 0xffff 42 #define PWCR_D 0x0000 43 #define PXCR_D 0x7500 44 #define PYCR_D 0x0000 45 #define PZCR_D 0x5540 46 47 /* Pin Function Controler data */ 48 #define PSELA_D 0x1410 49 #define PSELB_D 0x0140 50 #define PSELC_D 0x0000 51 #define PSELD_D 0x0400 52 53 /* I/O Buffer Hi-Z data */ 54 #define HIZCRA_D 0x0000 55 #define HIZCRB_D 0x1000 56 #define HIZCRC_D 0x0000 57 #define HIZCRD_D 0x0000 58 59 /* Module select reg data */ 60 #define MSELCRA_D 0x0014 61 #define MSELCRB_D 0x0018 62 63 /* Module Stop reg Data */ 64 #define MSTPCR2_D 0xFFD9F280 65 66 /* CPLD loader */ 67 extern void init_cpld(void); 68 69 int checkboard(void) 70 { 71 puts("BOARD: AP325RXA\n"); 72 return 0; 73 } 74 75 int board_init(void) 76 { 77 /* Pin Function Controler Init */ 78 outw(PSELA_D, PSELA); 79 outw(PSELB_D, PSELB); 80 outw(PSELC_D, PSELC); 81 outw(PSELD_D, PSELD); 82 83 /* I/O Buffer Hi-Z Init */ 84 outw(HIZCRA_D, HIZCRA); 85 outw(HIZCRB_D, HIZCRB); 86 outw(HIZCRC_D, HIZCRC); 87 outw(HIZCRD_D, HIZCRD); 88 89 /* Module select reg Init */ 90 outw(MSELCRA_D, MSELCRA); 91 outw(MSELCRB_D, MSELCRB); 92 93 /* Module Stop reg Init */ 94 outl(MSTPCR2_D, MSTPCR2); 95 96 /* I/O ports */ 97 outw(PACR_D, PACR); 98 outw(PBCR_D, PBCR); 99 outw(PCCR_D, PCCR); 100 outw(PDCR_D, PDCR); 101 outw(PECR_D, PECR); 102 outw(PFCR_D, PFCR); 103 outw(PGCR_D, PGCR); 104 outw(PHCR_D, PHCR); 105 outw(PJCR_D, PJCR); 106 outw(PKCR_D, PKCR); 107 outw(PLCR_D, PLCR); 108 outw(PMCR_D, PMCR); 109 outw(PNCR_D, PNCR); 110 outw(PQCR_D, PQCR); 111 outw(PRCR_D, PRCR); 112 outw(PSCR_D, PSCR); 113 outw(PTCR_D, PTCR); 114 outw(PUCR_D, PUCR); 115 outw(PVCR_D, PVCR); 116 outw(PWCR_D, PWCR); 117 outw(PXCR_D, PXCR); 118 outw(PYCR_D, PYCR); 119 outw(PZCR_D, PZCR); 120 121 /* PRI control register Init */ 122 outl(PRPRICR5_D, PRPRICR5); 123 124 /* cpld init */ 125 init_cpld(); 126 127 return 0; 128 } 129 130 void led_set_state(unsigned short value) 131 { 132 } 133 134 void ide_set_reset(int idereset) 135 { 136 outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ 137 udelay(FPGA_NAND_RST_WAIT); 138 outw(FPGA_NAND_INIT, FPGA_NAND_CTL); 139 } 140 141 int board_eth_init(bd_t *bis) 142 { 143 int rc = 0; 144 #ifdef CONFIG_SMC911X 145 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 146 #endif 147 return rc; 148 } 149