1 /* 2 * Copyright (C) 2008 Renesas Solutions Corp. 3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <netdev.h> 23 #include <asm/io.h> 24 #include <asm/processor.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 /* PRI control register */ 29 #define PRPRICR5 0xFF800048 /* LMB */ 30 #define PRPRICR5_D 0x2a 31 32 /* FPGA control */ 33 #define FPGA_NAND_CTL 0xB410020C 34 #define FPGA_NAND_RST 0x0008 35 #define FPGA_NAND_INIT 0x0000 36 #define FPGA_NAND_RST_WAIT 10000 37 38 /* I/O port data */ 39 #define PACR_D 0x0000 40 #define PBCR_D 0x0000 41 #define PCCR_D 0x1000 42 #define PDCR_D 0x0000 43 #define PECR_D 0x0410 44 #define PFCR_D 0xffff 45 #define PGCR_D 0x0000 46 #define PHCR_D 0x5011 47 #define PJCR_D 0x4400 48 #define PKCR_D 0x7c00 49 #define PLCR_D 0x0000 50 #define PMCR_D 0x0000 51 #define PNCR_D 0x0000 52 #define PQCR_D 0x0000 53 #define PRCR_D 0x0000 54 #define PSCR_D 0x0000 55 #define PTCR_D 0x0010 56 #define PUCR_D 0x0fff 57 #define PVCR_D 0xffff 58 #define PWCR_D 0x0000 59 #define PXCR_D 0x7500 60 #define PYCR_D 0x0000 61 #define PZCR_D 0x5540 62 63 /* Pin Function Controler data */ 64 #define PSELA_D 0x1410 65 #define PSELB_D 0x0140 66 #define PSELC_D 0x0000 67 #define PSELD_D 0x0400 68 69 /* I/O Buffer Hi-Z data */ 70 #define HIZCRA_D 0x0000 71 #define HIZCRB_D 0x1000 72 #define HIZCRC_D 0x0000 73 #define HIZCRD_D 0x0000 74 75 /* Module select reg data */ 76 #define MSELCRA_D 0x0014 77 #define MSELCRB_D 0x0018 78 79 /* Module Stop reg Data */ 80 #define MSTPCR2_D 0xFFD9F280 81 82 /* CPLD loader */ 83 extern void init_cpld(void); 84 85 int checkboard(void) 86 { 87 puts("BOARD: AP325RXA\n"); 88 return 0; 89 } 90 91 int board_init(void) 92 { 93 /* Pin Function Controler Init */ 94 outw(PSELA_D, PSELA); 95 outw(PSELB_D, PSELB); 96 outw(PSELC_D, PSELC); 97 outw(PSELD_D, PSELD); 98 99 /* I/O Buffer Hi-Z Init */ 100 outw(HIZCRA_D, HIZCRA); 101 outw(HIZCRB_D, HIZCRB); 102 outw(HIZCRC_D, HIZCRC); 103 outw(HIZCRD_D, HIZCRD); 104 105 /* Module select reg Init */ 106 outw(MSELCRA_D, MSELCRA); 107 outw(MSELCRB_D, MSELCRB); 108 109 /* Module Stop reg Init */ 110 outl(MSTPCR2_D, MSTPCR2); 111 112 /* I/O ports */ 113 outw(PACR_D, PACR); 114 outw(PBCR_D, PBCR); 115 outw(PCCR_D, PCCR); 116 outw(PDCR_D, PDCR); 117 outw(PECR_D, PECR); 118 outw(PFCR_D, PFCR); 119 outw(PGCR_D, PGCR); 120 outw(PHCR_D, PHCR); 121 outw(PJCR_D, PJCR); 122 outw(PKCR_D, PKCR); 123 outw(PLCR_D, PLCR); 124 outw(PMCR_D, PMCR); 125 outw(PNCR_D, PNCR); 126 outw(PQCR_D, PQCR); 127 outw(PRCR_D, PRCR); 128 outw(PSCR_D, PSCR); 129 outw(PTCR_D, PTCR); 130 outw(PUCR_D, PUCR); 131 outw(PVCR_D, PVCR); 132 outw(PWCR_D, PWCR); 133 outw(PXCR_D, PXCR); 134 outw(PYCR_D, PYCR); 135 outw(PZCR_D, PZCR); 136 137 /* PRI control register Init */ 138 outl(PRPRICR5_D, PRPRICR5); 139 140 /* cpld init */ 141 init_cpld(); 142 143 return 0; 144 } 145 146 int dram_init(void) 147 { 148 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 149 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 150 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); 151 return 0; 152 } 153 154 void led_set_state(unsigned short value) 155 { 156 } 157 158 void ide_set_reset(int idereset) 159 { 160 outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ 161 udelay(FPGA_NAND_RST_WAIT); 162 outw(FPGA_NAND_INIT, FPGA_NAND_CTL); 163 } 164 165 int board_eth_init(bd_t *bis) 166 { 167 int rc = 0; 168 #ifdef CONFIG_SMC911X 169 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 170 #endif 171 return rc; 172 } 173