1 /* 2 * Copyright (C) 2008 Renesas Solutions Corp. 3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <netdev.h> 23 #include <asm/io.h> 24 #include <asm/processor.h> 25 26 /* PRI control register */ 27 #define PRPRICR5 0xFF800048 /* LMB */ 28 #define PRPRICR5_D 0x2a 29 30 /* FPGA control */ 31 #define FPGA_NAND_CTL 0xB410020C 32 #define FPGA_NAND_RST 0x0008 33 #define FPGA_NAND_INIT 0x0000 34 #define FPGA_NAND_RST_WAIT 10000 35 36 /* I/O port data */ 37 #define PACR_D 0x0000 38 #define PBCR_D 0x0000 39 #define PCCR_D 0x1000 40 #define PDCR_D 0x0000 41 #define PECR_D 0x0410 42 #define PFCR_D 0xffff 43 #define PGCR_D 0x0000 44 #define PHCR_D 0x5011 45 #define PJCR_D 0x4400 46 #define PKCR_D 0x7c00 47 #define PLCR_D 0x0000 48 #define PMCR_D 0x0000 49 #define PNCR_D 0x0000 50 #define PQCR_D 0x0000 51 #define PRCR_D 0x0000 52 #define PSCR_D 0x0000 53 #define PTCR_D 0x0010 54 #define PUCR_D 0x0fff 55 #define PVCR_D 0xffff 56 #define PWCR_D 0x0000 57 #define PXCR_D 0x7500 58 #define PYCR_D 0x0000 59 #define PZCR_D 0x5540 60 61 /* Pin Function Controler data */ 62 #define PSELA_D 0x1410 63 #define PSELB_D 0x0140 64 #define PSELC_D 0x0000 65 #define PSELD_D 0x0400 66 67 /* I/O Buffer Hi-Z data */ 68 #define HIZCRA_D 0x0000 69 #define HIZCRB_D 0x1000 70 #define HIZCRC_D 0x0000 71 #define HIZCRD_D 0x0000 72 73 /* Module select reg data */ 74 #define MSELCRA_D 0x0014 75 #define MSELCRB_D 0x0018 76 77 /* Module Stop reg Data */ 78 #define MSTPCR2_D 0xFFD9F280 79 80 /* CPLD loader */ 81 extern void init_cpld(void); 82 83 int checkboard(void) 84 { 85 puts("BOARD: AP325RXA\n"); 86 return 0; 87 } 88 89 int board_init(void) 90 { 91 /* Pin Function Controler Init */ 92 outw(PSELA_D, PSELA); 93 outw(PSELB_D, PSELB); 94 outw(PSELC_D, PSELC); 95 outw(PSELD_D, PSELD); 96 97 /* I/O Buffer Hi-Z Init */ 98 outw(HIZCRA_D, HIZCRA); 99 outw(HIZCRB_D, HIZCRB); 100 outw(HIZCRC_D, HIZCRC); 101 outw(HIZCRD_D, HIZCRD); 102 103 /* Module select reg Init */ 104 outw(MSELCRA_D, MSELCRA); 105 outw(MSELCRB_D, MSELCRB); 106 107 /* Module Stop reg Init */ 108 outl(MSTPCR2_D, MSTPCR2); 109 110 /* I/O ports */ 111 outw(PACR_D, PACR); 112 outw(PBCR_D, PBCR); 113 outw(PCCR_D, PCCR); 114 outw(PDCR_D, PDCR); 115 outw(PECR_D, PECR); 116 outw(PFCR_D, PFCR); 117 outw(PGCR_D, PGCR); 118 outw(PHCR_D, PHCR); 119 outw(PJCR_D, PJCR); 120 outw(PKCR_D, PKCR); 121 outw(PLCR_D, PLCR); 122 outw(PMCR_D, PMCR); 123 outw(PNCR_D, PNCR); 124 outw(PQCR_D, PQCR); 125 outw(PRCR_D, PRCR); 126 outw(PSCR_D, PSCR); 127 outw(PTCR_D, PTCR); 128 outw(PUCR_D, PUCR); 129 outw(PVCR_D, PVCR); 130 outw(PWCR_D, PWCR); 131 outw(PXCR_D, PXCR); 132 outw(PYCR_D, PYCR); 133 outw(PZCR_D, PZCR); 134 135 /* PRI control register Init */ 136 outl(PRPRICR5_D, PRPRICR5); 137 138 /* cpld init */ 139 init_cpld(); 140 141 return 0; 142 } 143 144 int dram_init(void) 145 { 146 DECLARE_GLOBAL_DATA_PTR; 147 148 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 149 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 150 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); 151 return 0; 152 } 153 154 void led_set_state(unsigned short value) 155 { 156 } 157 158 void ide_set_reset(int idereset) 159 { 160 outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ 161 udelay(FPGA_NAND_RST_WAIT); 162 outw(FPGA_NAND_INIT, FPGA_NAND_CTL); 163 } 164 165 int board_eth_init(bd_t *bis) 166 { 167 int rc = 0; 168 #ifdef CONFIG_SMC911X 169 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 170 #endif 171 return rc; 172 } 173