1/*
2 * Copyright (C) 2007-2008
3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 *
5 * Copyright (C) 2007
6 * Kenati Technologies, Inc.
7 *
8 * board/MigoR/lowlevel_init.S
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <version.h>
28
29#include <asm/processor.h>
30#include <asm/macro.h>
31
32/*
33 * Board specific low level init code, called _very_ early in the
34 * startup sequence. Relocation to SDRAM has not happened yet, no
35 * stack is available, bss section has not been initialised, etc.
36 *
37 * (Note: As no stack is available, no subroutines can be called...).
38 */
39
40	.global	lowlevel_init
41
42	.text
43	.align	2
44
45lowlevel_init:
46	write32	CCR_A, CCR_D		! Address of Cache Control Register
47					! Instruction Cache Invalidate
48
49	write32	MMUCR_A, MMUCR_D	! Address of MMU Control Register
50					! TI == TLB Invalidate bit
51
52	write32	MSTPCR0_A, MSTPCR0_D	! Address of Power Control Register 0
53
54	write32	MSTPCR2_A, MSTPCR2_D	! Address of Power Control Register 2
55
56	write16	PFC_PULCR_A, PFC_PULCR_D
57
58	write16	PFC_DRVCR_A, PFC_DRVCR_D
59
60	write16	SBSCR_A, SBSCR_D
61
62	write16	PSCR_A, PSCR_D
63
64	write16	RWTCSR_A, RWTCSR_D_1	! 0xA4520004 (Watchdog Control / Status Register)
65					! 0xA507 -> timer_STOP / WDT_CLK = max
66
67	write16	RWTCNT_A, RWTCNT_D	! 0xA4520000 (Watchdog Count Register)
68					! 0x5A00 -> Clear
69
70	write16	RWTCSR_A, RWTCSR_D_2	! 0xA4520004 (Watchdog Control / Status Register)
71					! 0xA504 -> timer_STOP / CLK = 500ms
72
73	write32	DLLFRQ_A, DLLFRQ_D	! 20080115
74					! 20080115
75
76	write32	FRQCR_A, FRQCR_D	! 0xA4150000 Frequency control register
77					! 20080115
78
79	write32	CCR_A, CCR_D_2		! Address of Cache Control Register
80					! ??
81
82bsc_init:
83	write32	CMNCR_A, CMNCR_D
84
85	write32	CS0BCR_A, CS0BCR_D
86
87	write32	CS4BCR_A, CS4BCR_D
88
89	write32	CS5ABCR_A, CS5ABCR_D
90
91	write32	CS5BBCR_A, CS5BBCR_D
92
93	write32	CS6ABCR_A, CS6ABCR_D
94
95	write32	CS0WCR_A, CS0WCR_D
96
97	write32	CS4WCR_A, CS4WCR_D
98
99	write32	CS5AWCR_A, CS5AWCR_D
100
101	write32	CS5BWCR_A, CS5BWCR_D
102
103	write32	CS6AWCR_A, CS6AWCR_D
104
105	! SDRAM initialization
106	write32	SDCR_A, SDCR_D
107
108	write32	SDWCR_A, SDWCR_D
109
110	write32	SDPCR_A, SDPCR_D
111
112	write32	RTCOR_A, RTCOR_D
113
114	write32	RTCNT_A, RTCNT_D
115
116	write32	RTCSR_A, RTCSR_D
117
118	write32	RFCR_A, RFCR_D
119
120	write8	SDMR3_A, SDMR3_D
121
122	! BL bit off (init = ON) (?!?)
123
124	stc	sr, r0				! BL bit off(init=ON)
125	mov.l	SR_MASK_D, r1
126	and	r1, r0
127	ldc	r0, sr
128
129	rts
130	mov	#0, r0
131
132	.align	4
133
134CCR_A:		.long	CCR
135MMUCR_A:	.long	MMUCR
136MSTPCR0_A:	.long	MSTPCR0
137MSTPCR2_A:	.long	MSTPCR2
138PFC_PULCR_A:	.long	PULCR
139PFC_DRVCR_A:	.long	DRVCR
140SBSCR_A:	.long	SBSCR
141PSCR_A:		.long	PSCR
142RWTCSR_A:	.long	RWTCSR
143RWTCNT_A:	.long	RWTCNT
144FRQCR_A:	.long	FRQCR
145PLLCR_A:	.long	PLLCR
146DLLFRQ_A:	.long	DLLFRQ
147
148CCR_D:		.long	0x00000800
149CCR_D_2:	.long	0x00000103
150MMUCR_D:	.long	0x00000004
151MSTPCR0_D:	.long	0x00001001
152MSTPCR2_D:	.long	0xffffffff
153PFC_PULCR_D:	.long	0x6000
154PFC_DRVCR_D:	.long	0x0464
155FRQCR_D:	.long	0x07033639
156PLLCR_D:	.long	0x00005000
157DLLFRQ_D:	.long	0x000004F6
158
159CMNCR_A:	.long	CMNCR
160CMNCR_D:	.long	0x0000001B
161CS0BCR_A:	.long	CS0BCR
162CS0BCR_D:	.long	0x24920400
163CS4BCR_A:	.long	CS4BCR
164CS4BCR_D:	.long	0x00003400
165CS5ABCR_A:	.long	CS5ABCR
166CS5ABCR_D:	.long	0x24920400
167CS5BBCR_A:	.long	CS5BBCR
168CS5BBCR_D:	.long	0x24920400
169CS6ABCR_A:	.long	CS6ABCR
170CS6ABCR_D:	.long	0x24920400
171
172CS0WCR_A:	.long	CS0WCR
173CS0WCR_D:	.long	0x00000380
174CS4WCR_A:	.long	CS4WCR
175CS4WCR_D:	.long	0x00110080
176CS5AWCR_A:	.long	CS5AWCR
177CS5AWCR_D:	.long	0x00000300
178CS5BWCR_A:	.long	CS5BWCR
179CS5BWCR_D:	.long	0x00000300
180CS6AWCR_A:	.long	CS6AWCR
181CS6AWCR_D:	.long	0x00000300
182
183SDCR_A:		.long	SBSC_SDCR
184SDCR_D:		.long	0x80160809
185SDWCR_A:	.long	SBSC_SDWCR
186SDWCR_D:	.long	0x0014450C
187SDPCR_A:	.long	SBSC_SDPCR
188SDPCR_D:	.long	0x00000087
189RTCOR_A:	.long	SBSC_RTCOR
190RTCNT_A:	.long	SBSC_RTCNT
191RTCNT_D:	.long	0xA55A0012
192RTCOR_D:	.long	0xA55A001C
193RTCSR_A:	.long	SBSC_RTCSR
194RFCR_A:		.long	SBSC_RFCR
195RFCR_D:		.long	0xA55A0221
196RTCSR_D:	.long	0xA55A009a
197SDMR3_A:	.long	0xFE581180
198SDMR3_D:	.long	0x0
199
200SR_MASK_D:	.long	0xEFFFFF0F
201
202	.align	2
203
204SBSCR_D:	.word	0x0044
205PSCR_D:		.word	0x0000
206RWTCSR_D_1:	.word	0xA507
207RWTCSR_D_2:	.word	0xA504
208RWTCNT_D:	.word	0x5A00
209