1#
2# Copyright (C) 2011-2012
3# Gerald Kerma <dreagle@doukki.net>
4# Simon Baatz <gmbnomis@gmail.com>
5# Luka Perkov <luka@openwrt.org>
6#
7# See file CREDITS for list of people who contributed to this
8# project.
9#
10# This program is free software; you can redistribute it and/or
11# modify it under the terms of the GNU General Public License as
12# published by the Free Software Foundation; either version 2 of
13# the License, or (at your option) any later version.
14#
15# This program is distributed in the hope that it will be useful,
16# but WITHOUT ANY WARRANTY; without even the implied warranty of
17# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18# GNU General Public License for more details.
19#
20# You should have received a copy of the GNU General Public License
21# along with this program. If not, see <http://www.gnu.org/licenses/>.
22#
23# Refer doc/README.kwbimage for more details about how-to configure
24# and create kirkwood boot image
25#
26
27# Boot Media configurations
28BOOT_FROM	nand	# change from nand to uart if building UART image
29NAND_ECC_MODE	default
30NAND_PAGE_SIZE	0x0800
31
32# SOC registers configuration using bootrom header extension
33# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
34
35# Configure RGMII-0 interface pad voltage to 1.8V
36DATA 0xffd100e0 0x1b1b1b9b
37
38#Dram initalization for SINGLE x16 CL=5 @ 400MHz
39DATA 0xffd01400 0x43000c30	# DDR Configuration register
40# bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
41# bit23-14: 0x0,
42# bit24:    0x1,     enable exit self refresh mode on DDR access
43# bit25:    0x1,     required
44# bit29-26: 0x0,
45# bit31-30: 0x1,
46
47DATA 0xffd01404 0x37543000	# DDR Controller Control Low
48# bit4:     0x0, addr/cmd in smame cycle
49# bit5:     0x0, clk is driven during self refresh, we don't care for APX
50# bit6:     0x0, use recommended falling edge of clk for addr/cmd
51# bit14:    0x0, input buffer always powered up
52# bit18:    0x1, cpu lock transaction enabled
53# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
54# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
55# bit30-28: 0x3, required
56# bit31:    0x0, no additional STARTBURST delay
57
58DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
59# bit3-0:   TRAS lsbs
60# bit7-4:   TRCD
61# bit11-8:  TRP
62# bit15-12: TWR
63# bit19-16: TWTR
64# bit20:    TRAS msb
65# bit23-21: 0x0
66# bit27-24: TRRD
67# bit31-28: TRTP
68
69DATA 0xffd0140c 0x00000a33	# DDR Timing (High)
70# bit6-0:   TRFC
71# bit8-7:   TR2R
72# bit10-9:  TR2W
73# bit12-11: TW2W
74# bit31-13: 0x0, required
75
76DATA 0xffd01410 0x0000000c	# DDR Address Control
77# bit1-0:   00,  Cs0width (x8)
78# bit3-2:   11,  Cs0size (1Gb)
79# bit5-4:   00,  Cs1width (x8)
80# bit7-6:   11,  Cs1size (1Gb)
81# bit9-8:   00,  Cs2width (nonexistent
82# bit11-10: 00,  Cs2size  (nonexistent
83# bit13-12: 00,  Cs3width (nonexistent
84# bit15-14: 00,  Cs3size  (nonexistent
85# bit16:    0,   Cs0AddrSel
86# bit17:    0,   Cs1AddrSel
87# bit18:    0,   Cs2AddrSel
88# bit19:    0,   Cs3AddrSel
89# bit31-20: 0x0, required
90
91DATA 0xffd01414 0x00000000	# DDR Open Pages Control
92# bit0:    0,   OpenPage enabled
93# bit31-1: 0x0, required
94
95DATA 0xffd01418 0x00000000	# DDR Operation
96# bit3-0:   0x0, DDR cmd
97# bit31-4:  0x0, required
98
99DATA 0xffd0141c 0x00000c52	# DDR Mode
100# bit2-0:   0x2, BurstLen=2 required
101# bit3:     0x0, BurstType=0 required
102# bit6-4:   0x4, CL=5
103# bit7:     0x0, TestMode=0 normal
104# bit8:     0x0, DLL reset=0 normal
105# bit11-9:  0x6, auto-precharge write recovery ????????????
106# bit12:    0x0, PD must be zero
107# bit31-13: 0x0, required
108
109DATA 0xffd01420 0x00000040	# DDR Extended Mode
110# bit0:     0,   DDR DLL enabled
111# bit1:     0,   DDR drive strenght normal
112# bit2:     1,   DDR ODT control lsd (disabled)
113# bit5-3:   0x0, required
114# bit6:     0,   DDR ODT control msb, (disabled)
115# bit9-7:   0x0, required
116# bit10:    0,   differential DQS enabled
117# bit11:    0,   required
118# bit12:    0,   DDR output buffer enabled
119# bit31-13: 0x0, required
120
121DATA 0xffd01424 0x0000f17f	# DDR Controller Control High
122# bit2-0:   0x7, required
123# bit3:     0x1, MBUS Burst Chop disabled
124# bit6-4:   0x7, required
125# bit7:     0x0,
126# bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
127# bit9:     0x0, no half clock cycle addition to dataout
128# bit10:    0x0, 1/4 clock cycle skew enabled for addr/ctl signals
129# bit11:    0x0, 1/4 clock cycle skew disabled for write mesh
130# bit15-12: 0xf, required
131# bit31-16: 0,   required
132
133DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
134DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)
135
136DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
137DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
138# bit0:     0x1,     Window enabled
139# bit1:     0x0,     Write Protect disabled
140# bit3-2:   0x0,     CS0 hit selected
141# bit23-4:  0xfffff, required
142# bit31-24: 0x0f,    Size (i.e. 256MB)
143
144DATA 0xffd01508 0x10000000	# CS[1]n Base address to 256Mb
145DATA 0xffd0150c 0x00000000	# CS[1]n Size, window disabled
146
147DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
148DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled
149
150DATA 0xffd01494 0x00030000	# DDR ODT Control (Low)
151# bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
152# bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
153# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
154# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
155
156DATA 0xffd01498 0x00000000	# DDR ODT Control (High)
157# bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
158# bit3-2:  0x1, ODT1 active NEVER!
159# bit31-4: 0x0, required
160
161DATA 0xffd0149c 0x0000e803	# CPU ODT Control
162DATA 0xffd01480 0x00000001	# DDR Initialization Control
163# bit0: 0x1, enable DDR init upon this register write
164
165DATA 0xFFD20134 0x66666666      # L2 RAM Timing 0 Register
166DATA 0xFFD20138 0x66666666      # L2 RAM Timing 1 Register
167
168# End of Header extension
169DATA 0x0 0x0
170