1 /* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/addrspace.h> 10 #include <asm/types.h> 11 #include <mach/ar71xx_regs.h> 12 #include <mach/ddr.h> 13 #include <debug_uart.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 18 void board_debug_uart_init(void) 19 { 20 void __iomem *regs; 21 u32 val; 22 23 regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, 24 MAP_NOCACHE); 25 26 /* 27 * GPIO9 as input, GPIO10 as output 28 */ 29 val = readl(regs + AR71XX_GPIO_REG_OE); 30 val |= QCA953X_GPIO(9); 31 val &= ~QCA953X_GPIO(10); 32 writel(val, regs + AR71XX_GPIO_REG_OE); 33 34 /* 35 * Enable GPIO10 as UART0_SOUT 36 */ 37 val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); 38 val &= ~QCA953X_GPIO_MUX_MASK(16); 39 val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; 40 writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); 41 42 /* 43 * Enable GPIO9 as UART0_SIN 44 */ 45 val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); 46 val &= ~QCA953X_GPIO_MUX_MASK(8); 47 val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; 48 writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); 49 50 /* 51 * Enable GPIO10 output 52 */ 53 val = readl(regs + AR71XX_GPIO_REG_OUT); 54 val |= QCA953X_GPIO(10); 55 writel(val, regs + AR71XX_GPIO_REG_OUT); 56 } 57 #endif 58 59 int board_early_init_f(void) 60 { 61 #ifdef CONFIG_DEBUG_UART 62 debug_uart_init(); 63 #endif 64 ddr_init(); 65 return 0; 66 } 67