1 /* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/addrspace.h> 10 #include <asm/types.h> 11 #include <mach/ar71xx_regs.h> 12 #include <mach/ddr.h> 13 #include <mach/ath79.h> 14 #include <debug_uart.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 19 void board_debug_uart_init(void) 20 { 21 void __iomem *regs; 22 u32 val; 23 24 regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, 25 MAP_NOCACHE); 26 27 /* 28 * GPIO9 as input, GPIO10 as output 29 */ 30 val = readl(regs + AR71XX_GPIO_REG_OE); 31 val |= QCA953X_GPIO(9); 32 val &= ~QCA953X_GPIO(10); 33 writel(val, regs + AR71XX_GPIO_REG_OE); 34 35 /* 36 * Enable GPIO10 as UART0_SOUT 37 */ 38 val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); 39 val &= ~QCA953X_GPIO_MUX_MASK(16); 40 val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; 41 writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); 42 43 /* 44 * Enable GPIO9 as UART0_SIN 45 */ 46 val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); 47 val &= ~QCA953X_GPIO_MUX_MASK(8); 48 val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; 49 writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); 50 51 /* 52 * Enable GPIO10 output 53 */ 54 val = readl(regs + AR71XX_GPIO_REG_OUT); 55 val |= QCA953X_GPIO(10); 56 writel(val, regs + AR71XX_GPIO_REG_OUT); 57 } 58 #endif 59 60 int board_early_init_f(void) 61 { 62 #ifdef CONFIG_DEBUG_UART 63 debug_uart_init(); 64 #endif 65 ddr_init(); 66 ath79_eth_reset(); 67 return 0; 68 } 69