1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a2277cc3SWills Wang /* 3a2277cc3SWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 4a2277cc3SWills Wang */ 5a2277cc3SWills Wang 6a2277cc3SWills Wang #include <common.h> 7a2277cc3SWills Wang #include <asm/io.h> 8a2277cc3SWills Wang #include <asm/addrspace.h> 9a2277cc3SWills Wang #include <asm/types.h> 10a2277cc3SWills Wang #include <mach/ar71xx_regs.h> 11a2277cc3SWills Wang #include <mach/ddr.h> 12f1b65c98SWills Wang #include <mach/ath79.h> 13a2277cc3SWills Wang #include <debug_uart.h> 14a2277cc3SWills Wang 15a2277cc3SWills Wang #ifdef CONFIG_DEBUG_UART_BOARD_INIT board_debug_uart_init(void)16a2277cc3SWills Wangvoid board_debug_uart_init(void) 17a2277cc3SWills Wang { 18a2277cc3SWills Wang void __iomem *regs; 19a2277cc3SWills Wang u32 val; 20a2277cc3SWills Wang 21a2277cc3SWills Wang regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, 22a2277cc3SWills Wang MAP_NOCACHE); 23a2277cc3SWills Wang 24a2277cc3SWills Wang /* 25a2277cc3SWills Wang * GPIO9 as input, GPIO10 as output 26a2277cc3SWills Wang */ 27a2277cc3SWills Wang val = readl(regs + AR71XX_GPIO_REG_OE); 28a2277cc3SWills Wang val |= QCA953X_GPIO(9); 29a2277cc3SWills Wang val &= ~QCA953X_GPIO(10); 30a2277cc3SWills Wang writel(val, regs + AR71XX_GPIO_REG_OE); 31a2277cc3SWills Wang 32a2277cc3SWills Wang /* 33a2277cc3SWills Wang * Enable GPIO10 as UART0_SOUT 34a2277cc3SWills Wang */ 35a2277cc3SWills Wang val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); 36a2277cc3SWills Wang val &= ~QCA953X_GPIO_MUX_MASK(16); 37a2277cc3SWills Wang val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; 38a2277cc3SWills Wang writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); 39a2277cc3SWills Wang 40a2277cc3SWills Wang /* 41a2277cc3SWills Wang * Enable GPIO9 as UART0_SIN 42a2277cc3SWills Wang */ 43a2277cc3SWills Wang val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); 44a2277cc3SWills Wang val &= ~QCA953X_GPIO_MUX_MASK(8); 45a2277cc3SWills Wang val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; 46a2277cc3SWills Wang writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); 47a2277cc3SWills Wang 48a2277cc3SWills Wang /* 49a2277cc3SWills Wang * Enable GPIO10 output 50a2277cc3SWills Wang */ 51a2277cc3SWills Wang val = readl(regs + AR71XX_GPIO_REG_OUT); 52a2277cc3SWills Wang val |= QCA953X_GPIO(10); 53a2277cc3SWills Wang writel(val, regs + AR71XX_GPIO_REG_OUT); 54a2277cc3SWills Wang } 55a2277cc3SWills Wang #endif 56a2277cc3SWills Wang board_early_init_f(void)57a2277cc3SWills Wangint board_early_init_f(void) 58a2277cc3SWills Wang { 59a2277cc3SWills Wang ddr_init(); 60f1b65c98SWills Wang ath79_eth_reset(); 61a2277cc3SWills Wang return 0; 62a2277cc3SWills Wang } 63