1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 26a7b52bcSWills Wang /* 36a7b52bcSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 46a7b52bcSWills Wang */ 56a7b52bcSWills Wang 66a7b52bcSWills Wang #include <common.h> 76a7b52bcSWills Wang #include <asm/io.h> 86a7b52bcSWills Wang #include <asm/addrspace.h> 96a7b52bcSWills Wang #include <asm/types.h> 106a7b52bcSWills Wang #include <mach/ar71xx_regs.h> 116a7b52bcSWills Wang #include <mach/ddr.h> 1204583c68SWills Wang #include <mach/ath79.h> 136a7b52bcSWills Wang #include <debug_uart.h> 146a7b52bcSWills Wang 156a7b52bcSWills Wang #ifdef CONFIG_DEBUG_UART_BOARD_INIT board_debug_uart_init(void)166a7b52bcSWills Wangvoid board_debug_uart_init(void) 176a7b52bcSWills Wang { 186a7b52bcSWills Wang void __iomem *regs; 196a7b52bcSWills Wang u32 val; 206a7b52bcSWills Wang 216a7b52bcSWills Wang regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, 226a7b52bcSWills Wang MAP_NOCACHE); 236a7b52bcSWills Wang 246a7b52bcSWills Wang /* 256a7b52bcSWills Wang * GPIO9 as input, GPIO10 as output 266a7b52bcSWills Wang */ 276a7b52bcSWills Wang val = readl(regs + AR71XX_GPIO_REG_OE); 286a7b52bcSWills Wang val &= ~AR933X_GPIO(9); 296a7b52bcSWills Wang val |= AR933X_GPIO(10); 306a7b52bcSWills Wang writel(val, regs + AR71XX_GPIO_REG_OE); 316a7b52bcSWills Wang 326a7b52bcSWills Wang /* 336a7b52bcSWills Wang * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO 346a7b52bcSWills Wang */ 356a7b52bcSWills Wang val = readl(regs + AR71XX_GPIO_REG_FUNC); 366a7b52bcSWills Wang val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE; 376a7b52bcSWills Wang writel(val, regs + AR71XX_GPIO_REG_FUNC); 386a7b52bcSWills Wang } 396a7b52bcSWills Wang #endif 406a7b52bcSWills Wang board_early_init_f(void)416a7b52bcSWills Wangint board_early_init_f(void) 426a7b52bcSWills Wang { 436a7b52bcSWills Wang ddr_init(); 4404583c68SWills Wang ath79_eth_reset(); 456a7b52bcSWills Wang return 0; 466a7b52bcSWills Wang } 47