1*f9727161SMarek Vasut /* 2*f9727161SMarek Vasut * PPC-AG BG0900 Boot setup 3*f9727161SMarek Vasut * 4*f9727161SMarek Vasut * Copyright (C) 2013 Marek Vasut <marex@denx.de> 5*f9727161SMarek Vasut * 6*f9727161SMarek Vasut * SPDX-License-Identifier: GPL-2.0+ 7*f9727161SMarek Vasut */ 8*f9727161SMarek Vasut 9*f9727161SMarek Vasut #include <common.h> 10*f9727161SMarek Vasut #include <config.h> 11*f9727161SMarek Vasut #include <asm/io.h> 12*f9727161SMarek Vasut #include <asm/arch/iomux-mx28.h> 13*f9727161SMarek Vasut #include <asm/arch/imx-regs.h> 14*f9727161SMarek Vasut #include <asm/arch/sys_proto.h> 15*f9727161SMarek Vasut 16*f9727161SMarek Vasut #define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) 17*f9727161SMarek Vasut #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 18*f9727161SMarek Vasut #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) 19*f9727161SMarek Vasut #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 20*f9727161SMarek Vasut 21*f9727161SMarek Vasut const iomux_cfg_t iomux_setup[] = { 22*f9727161SMarek Vasut /* DUART */ 23*f9727161SMarek Vasut MX28_PAD_PWM0__DUART_RX, 24*f9727161SMarek Vasut MX28_PAD_PWM1__DUART_TX, 25*f9727161SMarek Vasut 26*f9727161SMarek Vasut /* GPMI NAND */ 27*f9727161SMarek Vasut MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, 28*f9727161SMarek Vasut MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, 29*f9727161SMarek Vasut MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, 30*f9727161SMarek Vasut MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, 31*f9727161SMarek Vasut MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, 32*f9727161SMarek Vasut MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, 33*f9727161SMarek Vasut MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, 34*f9727161SMarek Vasut MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, 35*f9727161SMarek Vasut MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, 36*f9727161SMarek Vasut MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, 37*f9727161SMarek Vasut MX28_PAD_GPMI_RDN__GPMI_RDN | 38*f9727161SMarek Vasut (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), 39*f9727161SMarek Vasut MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, 40*f9727161SMarek Vasut MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, 41*f9727161SMarek Vasut MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, 42*f9727161SMarek Vasut MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, 43*f9727161SMarek Vasut 44*f9727161SMarek Vasut /* FEC0 */ 45*f9727161SMarek Vasut MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, 46*f9727161SMarek Vasut MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, 47*f9727161SMarek Vasut MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, 48*f9727161SMarek Vasut MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, 49*f9727161SMarek Vasut MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, 50*f9727161SMarek Vasut MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, 51*f9727161SMarek Vasut MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, 52*f9727161SMarek Vasut MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, 53*f9727161SMarek Vasut MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, 54*f9727161SMarek Vasut 55*f9727161SMarek Vasut /* FEC0 Reset */ 56*f9727161SMarek Vasut MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | 57*f9727161SMarek Vasut (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 58*f9727161SMarek Vasut 59*f9727161SMarek Vasut /* EMI */ 60*f9727161SMarek Vasut MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, 61*f9727161SMarek Vasut MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, 62*f9727161SMarek Vasut MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, 63*f9727161SMarek Vasut MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, 64*f9727161SMarek Vasut MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, 65*f9727161SMarek Vasut MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, 66*f9727161SMarek Vasut MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, 67*f9727161SMarek Vasut MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, 68*f9727161SMarek Vasut MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, 69*f9727161SMarek Vasut MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, 70*f9727161SMarek Vasut MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, 71*f9727161SMarek Vasut MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, 72*f9727161SMarek Vasut MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, 73*f9727161SMarek Vasut MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, 74*f9727161SMarek Vasut MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, 75*f9727161SMarek Vasut MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, 76*f9727161SMarek Vasut MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, 77*f9727161SMarek Vasut MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, 78*f9727161SMarek Vasut MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, 79*f9727161SMarek Vasut MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, 80*f9727161SMarek Vasut MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, 81*f9727161SMarek Vasut MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, 82*f9727161SMarek Vasut MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, 83*f9727161SMarek Vasut MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, 84*f9727161SMarek Vasut MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, 85*f9727161SMarek Vasut 86*f9727161SMarek Vasut MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, 87*f9727161SMarek Vasut MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, 88*f9727161SMarek Vasut MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, 89*f9727161SMarek Vasut MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, 90*f9727161SMarek Vasut MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, 91*f9727161SMarek Vasut MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, 92*f9727161SMarek Vasut MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, 93*f9727161SMarek Vasut MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, 94*f9727161SMarek Vasut MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, 95*f9727161SMarek Vasut MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, 96*f9727161SMarek Vasut MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, 97*f9727161SMarek Vasut MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, 98*f9727161SMarek Vasut MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, 99*f9727161SMarek Vasut MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, 100*f9727161SMarek Vasut MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, 101*f9727161SMarek Vasut MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, 102*f9727161SMarek Vasut MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, 103*f9727161SMarek Vasut MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, 104*f9727161SMarek Vasut MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, 105*f9727161SMarek Vasut MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, 106*f9727161SMarek Vasut MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, 107*f9727161SMarek Vasut MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, 108*f9727161SMarek Vasut MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, 109*f9727161SMarek Vasut MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, 110*f9727161SMarek Vasut 111*f9727161SMarek Vasut /* SPI2 (for SPI flash) */ 112*f9727161SMarek Vasut MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, 113*f9727161SMarek Vasut MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, 114*f9727161SMarek Vasut MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, 115*f9727161SMarek Vasut MX28_PAD_SSP2_SS0__SSP2_D3 | 116*f9727161SMarek Vasut (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), 117*f9727161SMarek Vasut }; 118*f9727161SMarek Vasut 119*f9727161SMarek Vasut void mxs_adjust_memory_params(uint32_t *dram_vals) 120*f9727161SMarek Vasut { 121*f9727161SMarek Vasut dram_vals[0x98 / 4] = 0x04005003; 122*f9727161SMarek Vasut dram_vals[0x9c / 4] = 0x090000c8; 123*f9727161SMarek Vasut 124*f9727161SMarek Vasut dram_vals[0xa8 / 4] = 0x0036b009; 125*f9727161SMarek Vasut dram_vals[0xac / 4] = 0x03270612; 126*f9727161SMarek Vasut 127*f9727161SMarek Vasut dram_vals[0xb0 / 4] = 0x02020202; 128*f9727161SMarek Vasut dram_vals[0xb4 / 4] = 0x00c80029; 129*f9727161SMarek Vasut 130*f9727161SMarek Vasut dram_vals[0xc0 / 4] = 0x00011900; 131*f9727161SMarek Vasut 132*f9727161SMarek Vasut dram_vals[0x12c / 4] = 0x07400300; 133*f9727161SMarek Vasut dram_vals[0x130 / 4] = 0x07400300; 134*f9727161SMarek Vasut dram_vals[0x2c4 / 4] = 0x02030303; 135*f9727161SMarek Vasut } 136*f9727161SMarek Vasut 137*f9727161SMarek Vasut void board_init_ll(const uint32_t arg, const uint32_t *resptr) 138*f9727161SMarek Vasut { 139*f9727161SMarek Vasut mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); 140*f9727161SMarek Vasut } 141