1*f9727161SMarek Vasut /* 2*f9727161SMarek Vasut * PPC-AG BG0900 board 3*f9727161SMarek Vasut * 4*f9727161SMarek Vasut * Copyright (C) 2013 Marek Vasut <marex@denx.de> 5*f9727161SMarek Vasut * 6*f9727161SMarek Vasut * SPDX-License-Identifier: GPL-2.0+ 7*f9727161SMarek Vasut */ 8*f9727161SMarek Vasut 9*f9727161SMarek Vasut #include <common.h> 10*f9727161SMarek Vasut #include <asm/gpio.h> 11*f9727161SMarek Vasut #include <asm/io.h> 12*f9727161SMarek Vasut #include <asm/arch/imx-regs.h> 13*f9727161SMarek Vasut #include <asm/arch/iomux-mx28.h> 14*f9727161SMarek Vasut #include <asm/arch/clock.h> 15*f9727161SMarek Vasut #include <asm/arch/sys_proto.h> 16*f9727161SMarek Vasut #include <linux/mii.h> 17*f9727161SMarek Vasut #include <miiphy.h> 18*f9727161SMarek Vasut #include <netdev.h> 19*f9727161SMarek Vasut #include <errno.h> 20*f9727161SMarek Vasut 21*f9727161SMarek Vasut DECLARE_GLOBAL_DATA_PTR; 22*f9727161SMarek Vasut 23*f9727161SMarek Vasut /* 24*f9727161SMarek Vasut * Functions 25*f9727161SMarek Vasut */ 26*f9727161SMarek Vasut int board_early_init_f(void) 27*f9727161SMarek Vasut { 28*f9727161SMarek Vasut /* IO0 clock at 480MHz */ 29*f9727161SMarek Vasut mxs_set_ioclk(MXC_IOCLK0, 480000); 30*f9727161SMarek Vasut /* IO1 clock at 480MHz */ 31*f9727161SMarek Vasut mxs_set_ioclk(MXC_IOCLK1, 480000); 32*f9727161SMarek Vasut 33*f9727161SMarek Vasut /* SSP2 clock at 160MHz */ 34*f9727161SMarek Vasut mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); 35*f9727161SMarek Vasut 36*f9727161SMarek Vasut return 0; 37*f9727161SMarek Vasut } 38*f9727161SMarek Vasut 39*f9727161SMarek Vasut int dram_init(void) 40*f9727161SMarek Vasut { 41*f9727161SMarek Vasut return mxs_dram_init(); 42*f9727161SMarek Vasut } 43*f9727161SMarek Vasut 44*f9727161SMarek Vasut int board_init(void) 45*f9727161SMarek Vasut { 46*f9727161SMarek Vasut /* Adress of boot parameters */ 47*f9727161SMarek Vasut gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 48*f9727161SMarek Vasut 49*f9727161SMarek Vasut return 0; 50*f9727161SMarek Vasut } 51*f9727161SMarek Vasut 52*f9727161SMarek Vasut #ifdef CONFIG_CMD_NET 53*f9727161SMarek Vasut int board_eth_init(bd_t *bis) 54*f9727161SMarek Vasut { 55*f9727161SMarek Vasut struct mxs_clkctrl_regs *clkctrl_regs = 56*f9727161SMarek Vasut (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 57*f9727161SMarek Vasut struct eth_device *dev; 58*f9727161SMarek Vasut int ret; 59*f9727161SMarek Vasut 60*f9727161SMarek Vasut ret = cpu_eth_init(bis); 61*f9727161SMarek Vasut 62*f9727161SMarek Vasut /* BG0900 uses ENET_CLK PAD to drive FEC clock */ 63*f9727161SMarek Vasut writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, 64*f9727161SMarek Vasut &clkctrl_regs->hw_clkctrl_enet); 65*f9727161SMarek Vasut 66*f9727161SMarek Vasut /* Reset FEC PHYs */ 67*f9727161SMarek Vasut gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); 68*f9727161SMarek Vasut udelay(200); 69*f9727161SMarek Vasut gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); 70*f9727161SMarek Vasut 71*f9727161SMarek Vasut ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); 72*f9727161SMarek Vasut if (ret) { 73*f9727161SMarek Vasut puts("FEC MXS: Unable to init FEC0\n"); 74*f9727161SMarek Vasut return ret; 75*f9727161SMarek Vasut } 76*f9727161SMarek Vasut 77*f9727161SMarek Vasut dev = eth_get_dev_by_name("FEC0"); 78*f9727161SMarek Vasut if (!dev) { 79*f9727161SMarek Vasut puts("FEC MXS: Unable to get FEC0 device entry\n"); 80*f9727161SMarek Vasut return -EINVAL; 81*f9727161SMarek Vasut } 82*f9727161SMarek Vasut 83*f9727161SMarek Vasut return ret; 84*f9727161SMarek Vasut } 85*f9727161SMarek Vasut 86*f9727161SMarek Vasut #endif 87