1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2f9727161SMarek Vasut /* 3f9727161SMarek Vasut * PPC-AG BG0900 board 4f9727161SMarek Vasut * 5f9727161SMarek Vasut * Copyright (C) 2013 Marek Vasut <marex@denx.de> 6f9727161SMarek Vasut */ 7f9727161SMarek Vasut 8f9727161SMarek Vasut #include <common.h> 9f9727161SMarek Vasut #include <asm/gpio.h> 10f9727161SMarek Vasut #include <asm/io.h> 11f9727161SMarek Vasut #include <asm/arch/imx-regs.h> 12f9727161SMarek Vasut #include <asm/arch/iomux-mx28.h> 13f9727161SMarek Vasut #include <asm/arch/clock.h> 14f9727161SMarek Vasut #include <asm/arch/sys_proto.h> 15f9727161SMarek Vasut #include <linux/mii.h> 16f9727161SMarek Vasut #include <miiphy.h> 17f9727161SMarek Vasut #include <netdev.h> 18f9727161SMarek Vasut #include <errno.h> 19f9727161SMarek Vasut 20f9727161SMarek Vasut DECLARE_GLOBAL_DATA_PTR; 21f9727161SMarek Vasut 22f9727161SMarek Vasut /* 23f9727161SMarek Vasut * Functions 24f9727161SMarek Vasut */ 25f9727161SMarek Vasut int board_early_init_f(void) 26f9727161SMarek Vasut { 27f9727161SMarek Vasut /* IO0 clock at 480MHz */ 28f9727161SMarek Vasut mxs_set_ioclk(MXC_IOCLK0, 480000); 29f9727161SMarek Vasut /* IO1 clock at 480MHz */ 30f9727161SMarek Vasut mxs_set_ioclk(MXC_IOCLK1, 480000); 31f9727161SMarek Vasut 32f9727161SMarek Vasut /* SSP2 clock at 160MHz */ 33f9727161SMarek Vasut mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); 34f9727161SMarek Vasut 35f9727161SMarek Vasut return 0; 36f9727161SMarek Vasut } 37f9727161SMarek Vasut 38f9727161SMarek Vasut int dram_init(void) 39f9727161SMarek Vasut { 40f9727161SMarek Vasut return mxs_dram_init(); 41f9727161SMarek Vasut } 42f9727161SMarek Vasut 43f9727161SMarek Vasut int board_init(void) 44f9727161SMarek Vasut { 45f9727161SMarek Vasut /* Adress of boot parameters */ 46f9727161SMarek Vasut gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 47f9727161SMarek Vasut 48f9727161SMarek Vasut return 0; 49f9727161SMarek Vasut } 50f9727161SMarek Vasut 51f9727161SMarek Vasut #ifdef CONFIG_CMD_NET 52f9727161SMarek Vasut int board_eth_init(bd_t *bis) 53f9727161SMarek Vasut { 54f9727161SMarek Vasut struct mxs_clkctrl_regs *clkctrl_regs = 55f9727161SMarek Vasut (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 56f9727161SMarek Vasut struct eth_device *dev; 57f9727161SMarek Vasut int ret; 58f9727161SMarek Vasut 59f9727161SMarek Vasut ret = cpu_eth_init(bis); 60f9727161SMarek Vasut 61f9727161SMarek Vasut /* BG0900 uses ENET_CLK PAD to drive FEC clock */ 62f9727161SMarek Vasut writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, 63f9727161SMarek Vasut &clkctrl_regs->hw_clkctrl_enet); 64f9727161SMarek Vasut 65f9727161SMarek Vasut /* Reset FEC PHYs */ 66f9727161SMarek Vasut gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); 67f9727161SMarek Vasut udelay(200); 68f9727161SMarek Vasut gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); 69f9727161SMarek Vasut 70f9727161SMarek Vasut ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); 71f9727161SMarek Vasut if (ret) { 72f9727161SMarek Vasut puts("FEC MXS: Unable to init FEC0\n"); 73f9727161SMarek Vasut return ret; 74f9727161SMarek Vasut } 75f9727161SMarek Vasut 76f9727161SMarek Vasut dev = eth_get_dev_by_name("FEC0"); 77f9727161SMarek Vasut if (!dev) { 78f9727161SMarek Vasut puts("FEC MXS: Unable to get FEC0 device entry\n"); 79f9727161SMarek Vasut return -EINVAL; 80f9727161SMarek Vasut } 81f9727161SMarek Vasut 82f9727161SMarek Vasut return ret; 83f9727161SMarek Vasut } 84f9727161SMarek Vasut 85f9727161SMarek Vasut #endif 86