xref: /openbmc/u-boot/board/phytec/pcm058/pcm058.c (revision cbd2fba1)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
4  */
5 
6 /*
7  * Please note: there are two version of the board
8  * one with NAND and the other with eMMC.
9  * Both NAND and eMMC cannot be set because they share the
10  * same pins (SD4)
11  */
12 #include <common.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/mx6-ddr.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/mach-imx/spi.h>
24 #include <linux/errno.h>
25 #include <asm/gpio.h>
26 #include <mmc.h>
27 #include <i2c.h>
28 #include <fsl_esdhc.h>
29 #include <nand.h>
30 #include <miiphy.h>
31 #include <netdev.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/sections.h>
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
38 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
39 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
40 
41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
42 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
43 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
44 
45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
46 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47 
48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
49 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
50 
51 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
52 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
53 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
54 
55 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
56 
57 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP  |	\
58 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
59 
60 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
61 	       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62 
63 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
64 #define USDHC1_CD_GPIO	IMX_GPIO_NR(6, 31)
65 #define USER_LED	IMX_GPIO_NR(1, 4)
66 #define IMX6Q_DRIVE_STRENGTH	0x30
67 
68 int dram_init(void)
69 {
70 	gd->ram_size = imx_ddr_size();
71 	return 0;
72 }
73 
74 void board_turn_off_led(void)
75 {
76 	gpio_direction_output(USER_LED, 0);
77 }
78 
79 static iomux_v3_cfg_t const uart1_pads[] = {
80 	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
81 	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
82 };
83 
84 static iomux_v3_cfg_t const enet_pads[] = {
85 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
86 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
87 	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
88 	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
89 	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
90 	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
91 	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
92 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
93 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
94 	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
95 	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
96 	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
97 	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
98 	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
99 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
100 	MX6_PAD_SD2_DAT1__GPIO1_IO14	| MUX_PAD_CTRL(NO_PAD_CTRL),
101 };
102 
103 static iomux_v3_cfg_t const ecspi1_pads[] = {
104 	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
105 	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
106 	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
107 	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
108 };
109 
110 #ifdef CONFIG_CMD_NAND
111 /* NAND */
112 static iomux_v3_cfg_t const nfc_pads[] = {
113 	MX6_PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
114 	MX6_PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
115 	MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
116 	MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
117 	MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
118 	MX6_PAD_NANDF_CS1__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
119 	MX6_PAD_NANDF_CS2__NAND_CE2_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
120 	MX6_PAD_NANDF_CS3__NAND_CE3_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
121 	MX6_PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NAND_PAD_CTRL),
122 	MX6_PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NAND_PAD_CTRL),
123 	MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NAND_PAD_CTRL),
124 	MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NAND_PAD_CTRL),
125 	MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NAND_PAD_CTRL),
126 	MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NAND_PAD_CTRL),
127 	MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NAND_PAD_CTRL),
128 	MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NAND_PAD_CTRL),
129 	MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NAND_PAD_CTRL),
130 	MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NAND_PAD_CTRL),
131 	MX6_PAD_SD4_DAT0__NAND_DQS	| MUX_PAD_CTRL(NAND_PAD_CTRL),
132 };
133 #endif
134 
135 static struct i2c_pads_info i2c_pad_info2 = {
136 	.scl = {
137 		.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
138 		.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
139 		.gp = IMX_GPIO_NR(1, 5)
140 	},
141 	.sda = {
142 		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
143 		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
144 		.gp = IMX_GPIO_NR(1, 6)
145 	}
146 };
147 
148 static struct fsl_esdhc_cfg usdhc_cfg[] = {
149 	{.esdhc_base = USDHC1_BASE_ADDR,
150 	.max_bus_width = 4},
151 #ifndef CONFIG_CMD_NAND
152 	{USDHC4_BASE_ADDR},
153 #endif
154 };
155 
156 static iomux_v3_cfg_t const usdhc1_pads[] = {
157 	MX6_PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 	MX6_PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 	MX6_PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 	MX6_PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 	MX6_PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 	MX6_PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
164 };
165 
166 #if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
167 static iomux_v3_cfg_t const usdhc4_pads[] = {
168 	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
169 	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
170 	MX6_PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 	MX6_PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 	MX6_PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 	MX6_PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 	MX6_PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 	MX6_PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 	MX6_PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 	MX6_PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 };
179 #endif
180 
181 int board_mmc_get_env_dev(int devno)
182 {
183 	return devno - 1;
184 }
185 
186 int board_mmc_getcd(struct mmc *mmc)
187 {
188 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
189 	int ret = 0;
190 
191 	switch (cfg->esdhc_base) {
192 	case USDHC1_BASE_ADDR:
193 		ret = !gpio_get_value(USDHC1_CD_GPIO);
194 		break;
195 	case USDHC4_BASE_ADDR:
196 		ret = 1; /* eMMC/uSDHC4 is always present */
197 		break;
198 	}
199 
200 	return ret;
201 }
202 
203 int board_mmc_init(bd_t *bis)
204 {
205 #ifndef CONFIG_SPL_BUILD
206 	int ret;
207 	int i;
208 
209 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
210 		switch (i) {
211 		case 0:
212 			imx_iomux_v3_setup_multiple_pads(
213 				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
214 			gpio_direction_input(USDHC1_CD_GPIO);
215 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
216 			break;
217 #ifndef CONFIG_CMD_NAND
218 		case 1:
219 			imx_iomux_v3_setup_multiple_pads(
220 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
221 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
222 			break;
223 #endif
224 		default:
225 			printf("Warning: you configured more USDHC controllers"
226 			       "(%d) then supported by the board (%d)\n",
227 			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
228 			return -EINVAL;
229 		}
230 
231 		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
232 		if (ret)
233 			return ret;
234 	}
235 
236 	return 0;
237 #else
238 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
239 	unsigned reg = readl(&psrc->sbmr1) >> 11;
240 	/*
241 	 * Upon reading BOOT_CFG register the following map is done:
242 	 * Bit 11 and 12 of BOOT_CFG register can determine the current
243 	 * mmc port
244 	 * 0x1                  SD1
245 	 * 0x2                  SD2
246 	 * 0x3                  SD4
247 	 */
248 
249 	switch (reg & 0x3) {
250 	case 0x0:
251 		imx_iomux_v3_setup_multiple_pads(
252 			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
253 		gpio_direction_input(USDHC1_CD_GPIO);
254 		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
255 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
256 		usdhc_cfg[0].max_bus_width = 4;
257 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
258 		break;
259 	}
260 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
261 #endif
262 }
263 
264 static void setup_iomux_uart(void)
265 {
266 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
267 }
268 
269 static void setup_iomux_enet(void)
270 {
271 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
272 
273 	gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
274 	mdelay(10);
275 	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
276 	mdelay(30);
277 }
278 
279 static void setup_spi(void)
280 {
281 	gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
282 	gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
283 
284 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
285 
286 	enable_spi_clk(true, 0);
287 }
288 
289 #ifdef CONFIG_CMD_NAND
290 static void setup_gpmi_nand(void)
291 {
292 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
293 
294 	/* config gpmi nand iomux */
295 	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
296 
297 	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
298 	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
299 
300 	/* config gpmi and bch clock to 100 MHz */
301 	clrsetbits_le32(&mxc_ccm->cs2cdr,
302 			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
303 			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
304 			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
305 			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
306 			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
307 			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
308 
309 	/* enable ENFC_CLK_ROOT clock */
310 	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
311 
312 	/* enable gpmi and bch clock gating */
313 	setbits_le32(&mxc_ccm->CCGR4,
314 		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
315 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
316 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
317 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
318 		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
319 
320 	/* enable apbh clock gating */
321 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
322 }
323 #endif
324 
325 int board_spi_cs_gpio(unsigned bus, unsigned cs)
326 {
327 	if (bus != 0 || (cs != 0))
328 		return -EINVAL;
329 
330 	return IMX_GPIO_NR(3, 19);
331 }
332 
333 int board_eth_init(bd_t *bis)
334 {
335 	setup_iomux_enet();
336 
337 	return cpu_eth_init(bis);
338 }
339 
340 int board_early_init_f(void)
341 {
342 	setup_iomux_uart();
343 
344 	return 0;
345 }
346 
347 int board_init(void)
348 {
349 	/* address of boot parameters */
350 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
351 
352 #ifdef CONFIG_SYS_I2C_MXC
353 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
354 #endif
355 
356 #ifdef CONFIG_MXC_SPI
357 	setup_spi();
358 #endif
359 
360 #ifdef CONFIG_CMD_NAND
361 	setup_gpmi_nand();
362 #endif
363 	return 0;
364 }
365 
366 
367 #ifdef CONFIG_CMD_BMODE
368 /*
369  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
370  * see Table 8-11 and Table 5-9
371  *  BOOT_CFG1[7] = 1 (boot from NAND)
372  *  BOOT_CFG1[5] = 0 - raw NAND
373  *  BOOT_CFG1[4] = 0 - default pad settings
374  *  BOOT_CFG1[3:2] = 00 - devices = 1
375  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
376  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
377  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
378  *  BOOT_CFG2[0] = 0 - Reset time 12ms
379  */
380 static const struct boot_mode board_boot_modes[] = {
381 	/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
382 	{"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
383 	{"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
384 	{NULL, 0},
385 };
386 #endif
387 
388 int board_late_init(void)
389 {
390 #ifdef CONFIG_CMD_BMODE
391 	add_board_boot_modes(board_boot_modes);
392 #endif
393 
394 	return 0;
395 }
396 
397 #ifdef CONFIG_SPL_BUILD
398 #include <spl.h>
399 #include <linux/libfdt.h>
400 
401 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
402 	.dram_sdclk_0 = 0x00000030,
403 	.dram_sdclk_1 = 0x00000030,
404 	.dram_cas = 0x00000030,
405 	.dram_ras = 0x00000030,
406 	.dram_reset = 0x00000030,
407 	.dram_sdcke0 = 0x00000030,
408 	.dram_sdcke1 = 0x00000030,
409 	.dram_sdba2 = 0x00000000,
410 	.dram_sdodt0 = 0x00000030,
411 	.dram_sdodt1 = 0x00000030,
412 	.dram_sdqs0 = 0x00000030,
413 	.dram_sdqs1 = 0x00000030,
414 	.dram_sdqs2 = 0x00000030,
415 	.dram_sdqs3 = 0x00000030,
416 	.dram_sdqs4 = 0x00000030,
417 	.dram_sdqs5 = 0x00000030,
418 	.dram_sdqs6 = 0x00000030,
419 	.dram_sdqs7 = 0x00000030,
420 	.dram_dqm0 = 0x00000030,
421 	.dram_dqm1 = 0x00000030,
422 	.dram_dqm2 = 0x00000030,
423 	.dram_dqm3 = 0x00000030,
424 	.dram_dqm4 = 0x00000030,
425 	.dram_dqm5 = 0x00000030,
426 	.dram_dqm6 = 0x00000030,
427 	.dram_dqm7 = 0x00000030,
428 };
429 
430 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
431 	.grp_ddr_type =  0x000C0000,
432 	.grp_ddrmode_ctl =  0x00020000,
433 	.grp_ddrpke =  0x00000000,
434 	.grp_addds = IMX6Q_DRIVE_STRENGTH,
435 	.grp_ctlds = IMX6Q_DRIVE_STRENGTH,
436 	.grp_ddrmode =  0x00020000,
437 	.grp_b0ds = IMX6Q_DRIVE_STRENGTH,
438 	.grp_b1ds = IMX6Q_DRIVE_STRENGTH,
439 	.grp_b2ds = IMX6Q_DRIVE_STRENGTH,
440 	.grp_b3ds = IMX6Q_DRIVE_STRENGTH,
441 	.grp_b4ds = IMX6Q_DRIVE_STRENGTH,
442 	.grp_b5ds = IMX6Q_DRIVE_STRENGTH,
443 	.grp_b6ds = IMX6Q_DRIVE_STRENGTH,
444 	.grp_b7ds = IMX6Q_DRIVE_STRENGTH,
445 };
446 
447 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
448 	.p0_mpwldectrl0 =  0x00140014,
449 	.p0_mpwldectrl1 =  0x000A0015,
450 	.p1_mpwldectrl0 =  0x000A001E,
451 	.p1_mpwldectrl1 =  0x000A0015,
452 	.p0_mpdgctrl0 =  0x43080314,
453 	.p0_mpdgctrl1 =  0x02680300,
454 	.p1_mpdgctrl0 =  0x430C0318,
455 	.p1_mpdgctrl1 =  0x03000254,
456 	.p0_mprddlctl =  0x3A323234,
457 	.p1_mprddlctl =  0x3E3C3242,
458 	.p0_mpwrdlctl =  0x2A2E3632,
459 	.p1_mpwrdlctl =  0x3C323E34,
460 };
461 
462 static struct mx6_ddr3_cfg mem_ddr = {
463 	.mem_speed = 1600,
464 	.density = 2,
465 	.width = 16,
466 	.banks = 8,
467 	.rowaddr = 14,
468 	.coladdr = 10,
469 	.pagesz = 2,
470 	.trcd = 1375,
471 	.trcmin = 4875,
472 	.trasmin = 3500,
473 	.SRT       = 1,
474 };
475 
476 static void ccgr_init(void)
477 {
478 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
479 
480 	writel(0x00C03F3F, &ccm->CCGR0);
481 	writel(0x0030FC03, &ccm->CCGR1);
482 	writel(0x0FFFC000, &ccm->CCGR2);
483 	writel(0x3FF00000, &ccm->CCGR3);
484 	writel(0x00FFF300, &ccm->CCGR4);
485 	writel(0x0F0000C3, &ccm->CCGR5);
486 	writel(0x000003FF, &ccm->CCGR6);
487 }
488 
489 static void spl_dram_init(void)
490 {
491 	struct mx6_ddr_sysinfo sysinfo = {
492 		/* width of data bus:0=16,1=32,2=64 */
493 		.dsize = 2,
494 		/* config for full 4GB range so that get_mem_size() works */
495 		.cs_density = 32, /* 32Gb per CS */
496 		/* single chip select */
497 		.ncs = 1,
498 		.cs1_mirror = 0,
499 		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
500 		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
501 		.walat = 1,	/* Write additional latency */
502 		.ralat = 5,	/* Read additional latency */
503 		.mif3_mode = 3,	/* Command prediction working mode */
504 		.bi_on = 1,	/* Bank interleaving enabled */
505 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
506 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
507 		.ddr_type = DDR_TYPE_DDR3,
508 		.refsel = 1,	/* Refresh cycles at 32KHz */
509 		.refr = 7,	/* 8 refresh commands per refresh cycle */
510 	};
511 
512 	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
513 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
514 }
515 
516 void board_boot_order(u32 *spl_boot_list)
517 {
518 	spl_boot_list[0] = spl_boot_device();
519 	printf("Boot device %x\n", spl_boot_list[0]);
520 	switch (spl_boot_list[0]) {
521 	case BOOT_DEVICE_SPI:
522 		spl_boot_list[1] = BOOT_DEVICE_UART;
523 		break;
524 	case BOOT_DEVICE_MMC1:
525 		spl_boot_list[1] = BOOT_DEVICE_SPI;
526 		spl_boot_list[2] = BOOT_DEVICE_UART;
527 		break;
528 	default:
529 		printf("Boot device %x\n", spl_boot_list[0]);
530 	}
531 }
532 
533 void board_init_f(ulong dummy)
534 {
535 #ifdef CONFIG_CMD_NAND
536 	/* Enable NAND */
537 	setup_gpmi_nand();
538 #endif
539 
540 	/* setup clock gating */
541 	ccgr_init();
542 
543 	/* setup AIPS and disable watchdog */
544 	arch_cpu_init();
545 
546 	/* setup AXI */
547 	gpr_init();
548 
549 	board_early_init_f();
550 
551 	/* setup GP timer */
552 	timer_init();
553 
554 	setup_spi();
555 
556 	/* UART clocks enabled and gd valid - init serial console */
557 	preloader_console_init();
558 
559 	/* DDR initialization */
560 	spl_dram_init();
561 
562 	/* Clear the BSS. */
563 	memset(__bss_start, 0, __bss_end - __bss_start);
564 
565 	/* load/boot image from boot device */
566 	board_init_r(NULL, 0);
567 }
568 #endif
569