1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/iomux-vf610.h> 11 #include <asm/arch/ddrmc-vf610.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/clock.h> 14 #include <mmc.h> 15 #include <fsl_esdhc.h> 16 #include <miiphy.h> 17 #include <netdev.h> 18 #include <i2c.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* 23 * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h 24 * do not match our settings. Let us (re)define our own settings here. 25 */ 26 27 #define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm 28 #define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \ 29 PAD_CTL_INPUT_DIFFERENTIAL) 30 #define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \ 31 PAD_CTL_PUS_100K_UP | \ 32 PAD_CTL_INPUT_DIFFERENTIAL) 33 34 enum { 35 PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL), 36 PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 37 PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 38 PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 39 PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 40 PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 41 PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 42 PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 43 PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 44 PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 45 PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 46 PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 47 PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 48 PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 49 PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 50 PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 51 PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 52 PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 53 PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 54 PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 55 PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 56 PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 57 PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), 58 PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 59 PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 60 PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 61 PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 62 PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 63 PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 64 PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 65 PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 66 PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 67 PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 68 PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 69 PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 70 PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 71 PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 72 PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 73 PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 74 PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 75 PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 76 PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 77 PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), 78 PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), 79 PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 80 PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 81 PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 82 PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 83 PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 84 PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 85 }; 86 87 static struct ddrmc_cr_setting pcm052_cr_settings[] = { 88 /* not in the datasheets, but in the original code */ 89 { 0x00002000, 105 }, 90 { 0x00000020, 110 }, 91 /* AXI */ 92 { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 }, 93 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, 94 { DDRMC_CR120_AXI0_PRI1_RPRI(2) | 95 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, 96 { DDRMC_CR121_AXI0_PRI3_RPRI(2) | 97 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, 98 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | 99 DDRMC_CR122_AXI0_PRIRLX(100), 122 }, 100 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | 101 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, 102 { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, 103 { DDRMC_CR126_PHY_RDLAT(11), 126 }, 104 { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 }, 105 { DDRMC_CR137_PHYCTL_DL(2), 137 }, 106 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | 107 DDRMC_CR139_PHY_WRLV_DLL(3) | 108 DDRMC_CR139_PHY_WRLV_EN(3), 139 }, 109 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | 110 DDRMC_CR154_PAD_ZQ_MODE(1) | 111 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | 112 DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 }, 113 { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 }, 114 { DDRMC_CR158_TWR(6), 158 }, 115 { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) | 116 DDRMC_CR161_TODTH_WR(6), 161 }, 117 /* end marker */ 118 { 0, -1 } 119 }; 120 121 /* PHY settings -- most of them differ from default in imx-regs.h */ 122 123 #define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213 124 #define PCM052_DDRMC_PHY_CTRL 0x00290000 125 #define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00 126 #define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020 127 128 static struct ddrmc_phy_setting pcm052_phy_settings[] = { 129 { PCM052_DDRMC_PHY_DQ_TIMING, 0 }, 130 { PCM052_DDRMC_PHY_DQ_TIMING, 16 }, 131 { PCM052_DDRMC_PHY_DQ_TIMING, 32 }, 132 { PCM052_DDRMC_PHY_DQ_TIMING, 48 }, 133 { DDRMC_PHY_DQS_TIMING, 1 }, 134 { DDRMC_PHY_DQS_TIMING, 17 }, 135 { DDRMC_PHY_DQS_TIMING, 33 }, 136 { DDRMC_PHY_DQS_TIMING, 49 }, 137 { PCM052_DDRMC_PHY_CTRL, 2 }, 138 { PCM052_DDRMC_PHY_CTRL, 18 }, 139 { PCM052_DDRMC_PHY_CTRL, 34 }, 140 { DDRMC_PHY_MASTER_CTRL, 3 }, 141 { DDRMC_PHY_MASTER_CTRL, 19 }, 142 { DDRMC_PHY_MASTER_CTRL, 35 }, 143 { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 }, 144 { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 }, 145 { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 }, 146 { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 }, 147 { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 }, 148 149 /* end marker */ 150 { 0, -1 } 151 }; 152 153 int dram_init(void) 154 { 155 static const struct ddr3_jedec_timings pcm052_ddr_timings = { 156 .tinit = 5, 157 .trst_pwron = 80000, 158 .cke_inactive = 200000, 159 .wrlat = 5, 160 .caslat_lin = 12, 161 .trc = 6, 162 .trrd = 4, 163 .tccd = 4, 164 .tbst_int_interval = 4, 165 .tfaw = 18, 166 .trp = 6, 167 .twtr = 4, 168 .tras_min = 15, 169 .tmrd = 4, 170 .trtp = 4, 171 .tras_max = 14040, 172 .tmod = 12, 173 .tckesr = 4, 174 .tcke = 3, 175 .trcd_int = 6, 176 .tras_lockout = 1, 177 .tdal = 10, 178 .bstlen = 3, 179 .tdll = 512, 180 .trp_ab = 6, 181 .tref = 1542, 182 .trfc = 64, 183 .tref_int = 5, 184 .tpdex = 3, 185 .txpdll = 10, 186 .txsnr = 68, 187 .txsr = 506, 188 .cksrx = 5, 189 .cksre = 5, 190 .freq_chg_en = 1, 191 .zqcl = 256, 192 .zqinit = 512, 193 .zqcs = 64, 194 .ref_per_zq = 64, 195 .zqcs_rotate = 1, 196 .aprebit = 10, 197 .cmd_age_cnt = 255, 198 .age_cnt = 255, 199 .q_fullness = 0, 200 .odt_rd_mapcs0 = 1, 201 .odt_wr_mapcs0 = 1, 202 .wlmrd = 40, 203 .wldqsen = 25, 204 }; 205 206 static const iomux_v3_cfg_t pcm052_pads[] = { 207 PCM052_VF610_PAD_DDR_A15__DDR_A_15, 208 PCM052_VF610_PAD_DDR_A14__DDR_A_14, 209 PCM052_VF610_PAD_DDR_A13__DDR_A_13, 210 PCM052_VF610_PAD_DDR_A12__DDR_A_12, 211 PCM052_VF610_PAD_DDR_A11__DDR_A_11, 212 PCM052_VF610_PAD_DDR_A10__DDR_A_10, 213 PCM052_VF610_PAD_DDR_A9__DDR_A_9, 214 PCM052_VF610_PAD_DDR_A8__DDR_A_8, 215 PCM052_VF610_PAD_DDR_A7__DDR_A_7, 216 PCM052_VF610_PAD_DDR_A6__DDR_A_6, 217 PCM052_VF610_PAD_DDR_A5__DDR_A_5, 218 PCM052_VF610_PAD_DDR_A4__DDR_A_4, 219 PCM052_VF610_PAD_DDR_A3__DDR_A_3, 220 PCM052_VF610_PAD_DDR_A2__DDR_A_2, 221 PCM052_VF610_PAD_DDR_A1__DDR_A_1, 222 PCM052_VF610_PAD_DDR_A0__DDR_A_0, 223 PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, 224 PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, 225 PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, 226 PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, 227 PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, 228 PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, 229 PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, 230 PCM052_VF610_PAD_DDR_D15__DDR_D_15, 231 PCM052_VF610_PAD_DDR_D14__DDR_D_14, 232 PCM052_VF610_PAD_DDR_D13__DDR_D_13, 233 PCM052_VF610_PAD_DDR_D12__DDR_D_12, 234 PCM052_VF610_PAD_DDR_D11__DDR_D_11, 235 PCM052_VF610_PAD_DDR_D10__DDR_D_10, 236 PCM052_VF610_PAD_DDR_D9__DDR_D_9, 237 PCM052_VF610_PAD_DDR_D8__DDR_D_8, 238 PCM052_VF610_PAD_DDR_D7__DDR_D_7, 239 PCM052_VF610_PAD_DDR_D6__DDR_D_6, 240 PCM052_VF610_PAD_DDR_D5__DDR_D_5, 241 PCM052_VF610_PAD_DDR_D4__DDR_D_4, 242 PCM052_VF610_PAD_DDR_D3__DDR_D_3, 243 PCM052_VF610_PAD_DDR_D2__DDR_D_2, 244 PCM052_VF610_PAD_DDR_D1__DDR_D_1, 245 PCM052_VF610_PAD_DDR_D0__DDR_D_0, 246 PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, 247 PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, 248 PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, 249 PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, 250 PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, 251 PCM052_VF610_PAD_DDR_WE__DDR_WE_B, 252 PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, 253 PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, 254 PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, 255 PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, 256 PCM052_VF610_PAD_DDR_RESETB, 257 }; 258 259 imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); 260 261 ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, 262 pcm052_phy_settings, 1, 2); 263 264 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 265 266 return 0; 267 } 268 269 static void setup_iomux_uart(void) 270 { 271 static const iomux_v3_cfg_t uart1_pads[] = { 272 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), 273 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), 274 }; 275 276 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 277 } 278 279 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 280 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 281 282 static void setup_iomux_enet(void) 283 { 284 static const iomux_v3_cfg_t enet0_pads[] = { 285 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), 286 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), 287 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), 288 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), 289 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), 290 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), 291 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), 292 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), 293 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), 294 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), 295 }; 296 297 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 298 } 299 300 /* 301 * I2C2 is the only I2C used, on pads PTA22/PTA23. 302 */ 303 304 static void setup_iomux_i2c(void) 305 { 306 static const iomux_v3_cfg_t i2c_pads[] = { 307 VF610_PAD_PTA22__I2C2_SCL, 308 VF610_PAD_PTA23__I2C2_SDA, 309 }; 310 311 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); 312 } 313 314 #ifdef CONFIG_NAND_VF610_NFC 315 static void setup_iomux_nfc(void) 316 { 317 static const iomux_v3_cfg_t nfc_pads[] = { 318 VF610_PAD_PTD31__NF_IO15, 319 VF610_PAD_PTD30__NF_IO14, 320 VF610_PAD_PTD29__NF_IO13, 321 VF610_PAD_PTD28__NF_IO12, 322 VF610_PAD_PTD27__NF_IO11, 323 VF610_PAD_PTD26__NF_IO10, 324 VF610_PAD_PTD25__NF_IO9, 325 VF610_PAD_PTD24__NF_IO8, 326 VF610_PAD_PTD23__NF_IO7, 327 VF610_PAD_PTD22__NF_IO6, 328 VF610_PAD_PTD21__NF_IO5, 329 VF610_PAD_PTD20__NF_IO4, 330 VF610_PAD_PTD19__NF_IO3, 331 VF610_PAD_PTD18__NF_IO2, 332 VF610_PAD_PTD17__NF_IO1, 333 VF610_PAD_PTD16__NF_IO0, 334 VF610_PAD_PTB24__NF_WE_B, 335 VF610_PAD_PTB25__NF_CE0_B, 336 VF610_PAD_PTB27__NF_RE_B, 337 VF610_PAD_PTC26__NF_RB_B, 338 VF610_PAD_PTC27__NF_ALE, 339 VF610_PAD_PTC28__NF_CLE 340 }; 341 342 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 343 } 344 #endif 345 346 static void setup_iomux_qspi(void) 347 { 348 static const iomux_v3_cfg_t qspi0_pads[] = { 349 VF610_PAD_PTD0__QSPI0_A_QSCK, 350 VF610_PAD_PTD1__QSPI0_A_CS0, 351 VF610_PAD_PTD2__QSPI0_A_DATA3, 352 VF610_PAD_PTD3__QSPI0_A_DATA2, 353 VF610_PAD_PTD4__QSPI0_A_DATA1, 354 VF610_PAD_PTD5__QSPI0_A_DATA0, 355 VF610_PAD_PTD7__QSPI0_B_QSCK, 356 VF610_PAD_PTD8__QSPI0_B_CS0, 357 VF610_PAD_PTD9__QSPI0_B_DATA3, 358 VF610_PAD_PTD10__QSPI0_B_DATA2, 359 VF610_PAD_PTD11__QSPI0_B_DATA1, 360 VF610_PAD_PTD12__QSPI0_B_DATA0, 361 }; 362 363 imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); 364 } 365 366 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 367 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 368 369 struct fsl_esdhc_cfg esdhc_cfg[1] = { 370 {ESDHC1_BASE_ADDR}, 371 }; 372 373 int board_mmc_getcd(struct mmc *mmc) 374 { 375 /* eSDHC1 is always present */ 376 return 1; 377 } 378 379 int board_mmc_init(bd_t *bis) 380 { 381 static const iomux_v3_cfg_t esdhc1_pads[] = { 382 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 383 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 384 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 385 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 386 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 387 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 388 }; 389 390 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 391 392 imx_iomux_v3_setup_multiple_pads( 393 esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 394 395 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 396 } 397 398 static void clock_init(void) 399 { 400 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 401 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 402 403 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 404 CCM_CCGR0_UART1_CTRL_MASK); 405 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 406 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 407 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 408 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 409 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 410 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | 411 CCM_CCGR2_QSPI0_CTRL_MASK); 412 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 413 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); 414 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 415 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 416 CCM_CCGR4_GPC_CTRL_MASK); 417 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 418 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 419 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 420 CCM_CCGR7_SDHC1_CTRL_MASK); 421 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 422 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 423 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, 424 CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); 425 426 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, 427 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); 428 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 429 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 430 431 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 432 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 433 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, 434 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | 435 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | 436 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | 437 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | 438 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | 439 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); 440 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 441 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 442 CCM_CACRR_ARM_CLK_DIV(0)); 443 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 444 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | 445 CCM_CSCMR1_QSPI0_CLK_SEL(3) | 446 CCM_CSCMR1_NFC_CLK_SEL(0)); 447 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 448 CCM_CSCDR1_RMII_CLK_EN); 449 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 450 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | 451 CCM_CSCDR2_NFC_EN); 452 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 453 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | 454 CCM_CSCDR3_QSPI0_X2_DIV(1) | 455 CCM_CSCDR3_QSPI0_X4_DIV(3) | 456 CCM_CSCDR3_NFC_PRE_DIV(5)); 457 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 458 CCM_CSCMR2_RMII_CLK_SEL(0)); 459 } 460 461 static void mscm_init(void) 462 { 463 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 464 int i; 465 466 for (i = 0; i < MSCM_IRSPRC_NUM; i++) 467 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 468 } 469 470 int board_phy_config(struct phy_device *phydev) 471 { 472 if (phydev->drv->config) 473 phydev->drv->config(phydev); 474 475 return 0; 476 } 477 478 int board_early_init_f(void) 479 { 480 clock_init(); 481 mscm_init(); 482 setup_iomux_uart(); 483 setup_iomux_enet(); 484 setup_iomux_i2c(); 485 setup_iomux_qspi(); 486 setup_iomux_nfc(); 487 488 return 0; 489 } 490 491 int board_init(void) 492 { 493 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; 494 495 /* address of boot parameters */ 496 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 497 498 /* 499 * Enable external 32K Oscillator 500 * 501 * The internal clock experiences significant drift 502 * so we must use the external oscillator in order 503 * to maintain correct time in the hwclock 504 */ 505 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); 506 507 return 0; 508 } 509 510 int checkboard(void) 511 { 512 puts("Board: PCM-052\n"); 513 514 return 0; 515 } 516