1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/iomux-vf610.h> 11 #include <asm/arch/ddrmc-vf610.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/clock.h> 14 #include <mmc.h> 15 #include <fsl_esdhc.h> 16 #include <miiphy.h> 17 #include <netdev.h> 18 #include <i2c.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* 23 * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h 24 * do not match our settings. Let us (re)define our own settings here. 25 */ 26 27 #define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm 28 #define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \ 29 PAD_CTL_INPUT_DIFFERENTIAL) 30 #define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \ 31 PAD_CTL_PUS_100K_UP | \ 32 PAD_CTL_INPUT_DIFFERENTIAL) 33 34 enum { 35 PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL), 36 PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 37 PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 38 PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 39 PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 40 PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 41 PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 42 PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 43 PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 44 PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 45 PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 46 PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 47 PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 48 PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 49 PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 50 PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 51 PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 52 PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 53 PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 54 PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 55 PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 56 PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 57 PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), 58 PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 59 PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 60 PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 61 PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 62 PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 63 PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 64 PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 65 PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 66 PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 67 PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 68 PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 69 PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 70 PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 71 PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 72 PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 73 PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 74 PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 75 PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 76 PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 77 PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), 78 PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), 79 PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 80 PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 81 PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 82 PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 83 PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 84 PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), 85 }; 86 87 static struct ddrmc_cr_setting pcm052_cr_settings[] = { 88 /* not in the datasheets, but in the original code */ 89 { 0x00002000, 105 }, 90 { 0x00000020, 110 }, 91 /* AXI */ 92 { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 }, 93 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, 94 { DDRMC_CR120_AXI0_PRI1_RPRI(2) | 95 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, 96 { DDRMC_CR121_AXI0_PRI3_RPRI(2) | 97 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, 98 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | 99 DDRMC_CR122_AXI0_PRIRLX(100), 122 }, 100 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | 101 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, 102 { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, 103 { DDRMC_CR126_PHY_RDLAT(11), 126 }, 104 { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 }, 105 { DDRMC_CR137_PHYCTL_DL(2), 137 }, 106 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | 107 DDRMC_CR139_PHY_WRLV_DLL(3) | 108 DDRMC_CR139_PHY_WRLV_EN(3), 139 }, 109 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | 110 DDRMC_CR154_PAD_ZQ_MODE(1) | 111 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | 112 DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 }, 113 { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 }, 114 { DDRMC_CR158_TWR(6), 158 }, 115 { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) | 116 DDRMC_CR161_TODTH_WR(6), 161 }, 117 /* end marker */ 118 { 0, -1 } 119 }; 120 121 /* PHY settings -- most of them differ from default in imx-regs.h */ 122 123 #define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213 124 #define PCM052_DDRMC_PHY_CTRL 0x00290000 125 #define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00 126 #define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020 127 128 static struct ddrmc_phy_setting pcm052_phy_settings[] = { 129 { PCM052_DDRMC_PHY_DQ_TIMING, 0 }, 130 { PCM052_DDRMC_PHY_DQ_TIMING, 16 }, 131 { PCM052_DDRMC_PHY_DQ_TIMING, 32 }, 132 { PCM052_DDRMC_PHY_DQ_TIMING, 48 }, 133 { DDRMC_PHY_DQS_TIMING, 1 }, 134 { DDRMC_PHY_DQS_TIMING, 17 }, 135 { DDRMC_PHY_DQS_TIMING, 33 }, 136 { DDRMC_PHY_DQS_TIMING, 49 }, 137 { PCM052_DDRMC_PHY_CTRL, 2 }, 138 { PCM052_DDRMC_PHY_CTRL, 18 }, 139 { PCM052_DDRMC_PHY_CTRL, 34 }, 140 { DDRMC_PHY_MASTER_CTRL, 3 }, 141 { DDRMC_PHY_MASTER_CTRL, 19 }, 142 { DDRMC_PHY_MASTER_CTRL, 35 }, 143 { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 }, 144 { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 }, 145 { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 }, 146 { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 }, 147 { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 }, 148 149 /* end marker */ 150 { 0, -1 } 151 }; 152 153 int dram_init(void) 154 { 155 static const iomux_v3_cfg_t pcm052_pads[] = { 156 PCM052_VF610_PAD_DDR_A15__DDR_A_15, 157 PCM052_VF610_PAD_DDR_A14__DDR_A_14, 158 PCM052_VF610_PAD_DDR_A13__DDR_A_13, 159 PCM052_VF610_PAD_DDR_A12__DDR_A_12, 160 PCM052_VF610_PAD_DDR_A11__DDR_A_11, 161 PCM052_VF610_PAD_DDR_A10__DDR_A_10, 162 PCM052_VF610_PAD_DDR_A9__DDR_A_9, 163 PCM052_VF610_PAD_DDR_A8__DDR_A_8, 164 PCM052_VF610_PAD_DDR_A7__DDR_A_7, 165 PCM052_VF610_PAD_DDR_A6__DDR_A_6, 166 PCM052_VF610_PAD_DDR_A5__DDR_A_5, 167 PCM052_VF610_PAD_DDR_A4__DDR_A_4, 168 PCM052_VF610_PAD_DDR_A3__DDR_A_3, 169 PCM052_VF610_PAD_DDR_A2__DDR_A_2, 170 PCM052_VF610_PAD_DDR_A1__DDR_A_1, 171 PCM052_VF610_PAD_DDR_A0__DDR_A_0, 172 PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, 173 PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, 174 PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, 175 PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, 176 PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, 177 PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, 178 PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, 179 PCM052_VF610_PAD_DDR_D15__DDR_D_15, 180 PCM052_VF610_PAD_DDR_D14__DDR_D_14, 181 PCM052_VF610_PAD_DDR_D13__DDR_D_13, 182 PCM052_VF610_PAD_DDR_D12__DDR_D_12, 183 PCM052_VF610_PAD_DDR_D11__DDR_D_11, 184 PCM052_VF610_PAD_DDR_D10__DDR_D_10, 185 PCM052_VF610_PAD_DDR_D9__DDR_D_9, 186 PCM052_VF610_PAD_DDR_D8__DDR_D_8, 187 PCM052_VF610_PAD_DDR_D7__DDR_D_7, 188 PCM052_VF610_PAD_DDR_D6__DDR_D_6, 189 PCM052_VF610_PAD_DDR_D5__DDR_D_5, 190 PCM052_VF610_PAD_DDR_D4__DDR_D_4, 191 PCM052_VF610_PAD_DDR_D3__DDR_D_3, 192 PCM052_VF610_PAD_DDR_D2__DDR_D_2, 193 PCM052_VF610_PAD_DDR_D1__DDR_D_1, 194 PCM052_VF610_PAD_DDR_D0__DDR_D_0, 195 PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, 196 PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, 197 PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, 198 PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, 199 PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, 200 PCM052_VF610_PAD_DDR_WE__DDR_WE_B, 201 PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, 202 PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, 203 PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, 204 PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, 205 PCM052_VF610_PAD_DDR_RESETB, 206 }; 207 208 #if defined(CONFIG_TARGET_PCM052) 209 210 static const struct ddr3_jedec_timings pcm052_ddr_timings = { 211 .tinit = 5, 212 .trst_pwron = 80000, 213 .cke_inactive = 200000, 214 .wrlat = 5, 215 .caslat_lin = 12, 216 .trc = 6, 217 .trrd = 4, 218 .tccd = 4, 219 .tbst_int_interval = 4, 220 .tfaw = 18, 221 .trp = 6, 222 .twtr = 4, 223 .tras_min = 15, 224 .tmrd = 4, 225 .trtp = 4, 226 .tras_max = 14040, 227 .tmod = 12, 228 .tckesr = 4, 229 .tcke = 3, 230 .trcd_int = 6, 231 .tras_lockout = 1, 232 .tdal = 10, 233 .bstlen = 3, 234 .tdll = 512, 235 .trp_ab = 6, 236 .tref = 1542, 237 .trfc = 64, 238 .tref_int = 5, 239 .tpdex = 3, 240 .txpdll = 10, 241 .txsnr = 68, 242 .txsr = 506, 243 .cksrx = 5, 244 .cksre = 5, 245 .freq_chg_en = 1, 246 .zqcl = 256, 247 .zqinit = 512, 248 .zqcs = 64, 249 .ref_per_zq = 64, 250 .zqcs_rotate = 1, 251 .aprebit = 10, 252 .cmd_age_cnt = 255, 253 .age_cnt = 255, 254 .q_fullness = 0, 255 .odt_rd_mapcs0 = 1, 256 .odt_wr_mapcs0 = 1, 257 .wlmrd = 40, 258 .wldqsen = 25, 259 }; 260 261 ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, 262 pcm052_phy_settings, 1, 2); 263 264 #elif defined(CONFIG_TARGET_BK4R1) 265 266 static const struct ddr3_jedec_timings pcm052_ddr_timings = { 267 .tinit = 5, 268 .trst_pwron = 80000, 269 .cke_inactive = 200000, 270 .wrlat = 5, 271 .caslat_lin = 12, 272 .trc = 6, 273 .trrd = 4, 274 .tccd = 4, 275 .tbst_int_interval = 0, 276 .tfaw = 16, 277 .trp = 6, 278 .twtr = 4, 279 .tras_min = 15, 280 .tmrd = 4, 281 .trtp = 4, 282 .tras_max = 28080, 283 .tmod = 12, 284 .tckesr = 4, 285 .tcke = 3, 286 .trcd_int = 6, 287 .tras_lockout = 1, 288 .tdal = 12, 289 .bstlen = 3, 290 .tdll = 512, 291 .trp_ab = 6, 292 .tref = 3120, 293 .trfc = 104, 294 .tref_int = 0, 295 .tpdex = 3, 296 .txpdll = 10, 297 .txsnr = 108, 298 .txsr = 512, 299 .cksrx = 5, 300 .cksre = 5, 301 .freq_chg_en = 1, 302 .zqcl = 256, 303 .zqinit = 512, 304 .zqcs = 64, 305 .ref_per_zq = 64, 306 .zqcs_rotate = 1, 307 .aprebit = 10, 308 .cmd_age_cnt = 255, 309 .age_cnt = 255, 310 .q_fullness = 0, 311 .odt_rd_mapcs0 = 1, 312 .odt_wr_mapcs0 = 1, 313 .wlmrd = 40, 314 .wldqsen = 25, 315 }; 316 317 ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, 318 pcm052_phy_settings, 1, 1); 319 320 #else /* Unknown PCM052 variant */ 321 322 #error DDR characteristics undefined for this target. Please define them. 323 324 #endif 325 326 imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); 327 328 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 329 330 return 0; 331 } 332 333 static void setup_iomux_uart(void) 334 { 335 static const iomux_v3_cfg_t uart1_pads[] = { 336 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), 337 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), 338 }; 339 340 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 341 } 342 343 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 344 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 345 346 static void setup_iomux_enet(void) 347 { 348 static const iomux_v3_cfg_t enet0_pads[] = { 349 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), 350 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), 351 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), 352 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), 353 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), 354 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), 355 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), 356 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), 357 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), 358 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), 359 }; 360 361 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 362 } 363 364 /* 365 * I2C2 is the only I2C used, on pads PTA22/PTA23. 366 */ 367 368 static void setup_iomux_i2c(void) 369 { 370 static const iomux_v3_cfg_t i2c_pads[] = { 371 VF610_PAD_PTA22__I2C2_SCL, 372 VF610_PAD_PTA23__I2C2_SDA, 373 }; 374 375 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); 376 } 377 378 #ifdef CONFIG_NAND_VF610_NFC 379 static void setup_iomux_nfc(void) 380 { 381 static const iomux_v3_cfg_t nfc_pads[] = { 382 VF610_PAD_PTD31__NF_IO15, 383 VF610_PAD_PTD30__NF_IO14, 384 VF610_PAD_PTD29__NF_IO13, 385 VF610_PAD_PTD28__NF_IO12, 386 VF610_PAD_PTD27__NF_IO11, 387 VF610_PAD_PTD26__NF_IO10, 388 VF610_PAD_PTD25__NF_IO9, 389 VF610_PAD_PTD24__NF_IO8, 390 VF610_PAD_PTD23__NF_IO7, 391 VF610_PAD_PTD22__NF_IO6, 392 VF610_PAD_PTD21__NF_IO5, 393 VF610_PAD_PTD20__NF_IO4, 394 VF610_PAD_PTD19__NF_IO3, 395 VF610_PAD_PTD18__NF_IO2, 396 VF610_PAD_PTD17__NF_IO1, 397 VF610_PAD_PTD16__NF_IO0, 398 VF610_PAD_PTB24__NF_WE_B, 399 VF610_PAD_PTB25__NF_CE0_B, 400 VF610_PAD_PTB27__NF_RE_B, 401 VF610_PAD_PTC26__NF_RB_B, 402 VF610_PAD_PTC27__NF_ALE, 403 VF610_PAD_PTC28__NF_CLE 404 }; 405 406 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 407 } 408 #endif 409 410 static void setup_iomux_qspi(void) 411 { 412 static const iomux_v3_cfg_t qspi0_pads[] = { 413 VF610_PAD_PTD0__QSPI0_A_QSCK, 414 VF610_PAD_PTD1__QSPI0_A_CS0, 415 VF610_PAD_PTD2__QSPI0_A_DATA3, 416 VF610_PAD_PTD3__QSPI0_A_DATA2, 417 VF610_PAD_PTD4__QSPI0_A_DATA1, 418 VF610_PAD_PTD5__QSPI0_A_DATA0, 419 VF610_PAD_PTD7__QSPI0_B_QSCK, 420 VF610_PAD_PTD8__QSPI0_B_CS0, 421 VF610_PAD_PTD9__QSPI0_B_DATA3, 422 VF610_PAD_PTD10__QSPI0_B_DATA2, 423 VF610_PAD_PTD11__QSPI0_B_DATA1, 424 VF610_PAD_PTD12__QSPI0_B_DATA0, 425 }; 426 427 imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); 428 } 429 430 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 431 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 432 433 struct fsl_esdhc_cfg esdhc_cfg[1] = { 434 {ESDHC1_BASE_ADDR}, 435 }; 436 437 int board_mmc_getcd(struct mmc *mmc) 438 { 439 /* eSDHC1 is always present */ 440 return 1; 441 } 442 443 int board_mmc_init(bd_t *bis) 444 { 445 static const iomux_v3_cfg_t esdhc1_pads[] = { 446 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 447 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 448 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 449 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 450 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 451 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 452 }; 453 454 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 455 456 imx_iomux_v3_setup_multiple_pads( 457 esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 458 459 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 460 } 461 462 static void clock_init(void) 463 { 464 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 465 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 466 467 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 468 CCM_CCGR0_UART1_CTRL_MASK); 469 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 470 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 471 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 472 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 473 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 474 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | 475 CCM_CCGR2_QSPI0_CTRL_MASK); 476 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 477 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); 478 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 479 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 480 CCM_CCGR4_GPC_CTRL_MASK); 481 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 482 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 483 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 484 CCM_CCGR7_SDHC1_CTRL_MASK); 485 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 486 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 487 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, 488 CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); 489 490 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, 491 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); 492 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 493 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 494 495 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 496 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 497 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, 498 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | 499 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | 500 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | 501 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | 502 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | 503 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); 504 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 505 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 506 CCM_CACRR_ARM_CLK_DIV(0)); 507 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 508 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | 509 CCM_CSCMR1_QSPI0_CLK_SEL(3) | 510 CCM_CSCMR1_NFC_CLK_SEL(0)); 511 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 512 CCM_CSCDR1_RMII_CLK_EN); 513 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 514 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | 515 CCM_CSCDR2_NFC_EN); 516 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 517 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | 518 CCM_CSCDR3_QSPI0_X2_DIV(1) | 519 CCM_CSCDR3_QSPI0_X4_DIV(3) | 520 CCM_CSCDR3_NFC_PRE_DIV(5)); 521 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 522 CCM_CSCMR2_RMII_CLK_SEL(0)); 523 } 524 525 static void mscm_init(void) 526 { 527 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 528 int i; 529 530 for (i = 0; i < MSCM_IRSPRC_NUM; i++) 531 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 532 } 533 534 int board_phy_config(struct phy_device *phydev) 535 { 536 if (phydev->drv->config) 537 phydev->drv->config(phydev); 538 539 return 0; 540 } 541 542 int board_early_init_f(void) 543 { 544 clock_init(); 545 mscm_init(); 546 setup_iomux_uart(); 547 setup_iomux_enet(); 548 setup_iomux_i2c(); 549 setup_iomux_qspi(); 550 setup_iomux_nfc(); 551 552 return 0; 553 } 554 555 int board_init(void) 556 { 557 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; 558 559 /* address of boot parameters */ 560 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 561 562 /* 563 * Enable external 32K Oscillator 564 * 565 * The internal clock experiences significant drift 566 * so we must use the external oscillator in order 567 * to maintain correct time in the hwclock 568 */ 569 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); 570 571 return 0; 572 } 573 574 int checkboard(void) 575 { 576 puts("Board: PCM-052\n"); 577 578 return 0; 579 } 580 581 static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc, 582 char * const argv[]) 583 { 584 ulong addr; 585 586 /* Consume 'm4go' */ 587 argc--; argv++; 588 589 /* 590 * Parse provided address - default to load_addr in case not provided. 591 */ 592 593 if (argc) 594 addr = simple_strtoul(argv[0], NULL, 16); 595 else 596 addr = load_addr; 597 598 /* 599 * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0] 600 */ 601 writel(addr + 0x401, 0x4006E028); 602 603 /* 604 * Start secondary processor by enabling its clock 605 */ 606 writel(0x15a5a, 0x4006B08C); 607 608 return 1; 609 } 610 611 U_BOOT_CMD( 612 m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go, 613 "start the secondary Cortex-M4 from scatter file image", 614 "[<addr>]\n" 615 " - start secondary Cortex-M4 core using a scatter file image\n" 616 "The argument needs to be a scatter file\n" 617 ); 618