xref: /openbmc/u-boot/board/phytec/pcm051/mux.c (revision ed09a554)
1 /*
2  * mux.c
3  *
4  * Copyright (C) 2013 Lemonage Software GmbH
5  * Author Lars Poeschel <poeschel@lemonage.de>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <common.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/mux.h>
21 #include <asm/io.h>
22 #include "board.h"
23 
24 static struct module_pin_mux uart0_pin_mux[] = {
25 	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
26 	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
27 	{-1},
28 };
29 
30 #ifdef CONFIG_MMC
31 static struct module_pin_mux mmc0_pin_mux[] = {
32 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
33 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
34 	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
35 	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
36 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
37 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
38 	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
39 	{-1},
40 };
41 #endif
42 
43 #ifdef CONFIG_I2C
44 static struct module_pin_mux i2c0_pin_mux[] = {
45 	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
46 			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
47 	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
48 			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
49 	{-1},
50 };
51 #endif
52 
53 #ifdef CONFIG_SPI
54 static struct module_pin_mux spi0_pin_mux[] = {
55 	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
56 	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
57 			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
58 	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
59 	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
60 			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
61 	{-1},
62 };
63 #endif
64 
65 static struct module_pin_mux rmii1_pin_mux[] = {
66 	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},     /* RMII1_CRS */
67 	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},   /* RMII1_RXERR */
68 	{OFFSET(mii1_txen), MODE(1)},               /* RMII1_TXEN */
69 	{OFFSET(mii1_txd1), MODE(1)},               /* RMII1_TXD1 */
70 	{OFFSET(mii1_txd0), MODE(1)},               /* RMII1_TXD0 */
71 	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RXD1 */
72 	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RXD0 */
73 	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
74 	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
75 	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
76 	{-1},
77 };
78 
79 static struct module_pin_mux cbmux_pin_mux[] = {
80 	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
81 	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN},	/* JP4 */
82 	{-1},
83 };
84 
85 #ifdef CONFIG_NAND
86 static struct module_pin_mux nand_pin_mux[] = {
87 	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
88 	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
89 	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
90 	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
91 	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
92 	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
93 	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
94 	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
95 	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
96 	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
97 	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
98 	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
99 	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
100 	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
101 	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
102 	{-1},
103 };
104 #endif
105 
106 void enable_uart0_pin_mux(void)
107 {
108 	configure_module_pin_mux(uart0_pin_mux);
109 }
110 
111 void enable_i2c0_pin_mux(void)
112 {
113 	configure_module_pin_mux(i2c0_pin_mux);
114 }
115 
116 void enable_board_pin_mux()
117 {
118 	configure_module_pin_mux(rmii1_pin_mux);
119 	configure_module_pin_mux(mmc0_pin_mux);
120 	configure_module_pin_mux(cbmux_pin_mux);
121 #ifdef CONFIG_NAND
122 	configure_module_pin_mux(nand_pin_mux);
123 #endif
124 #ifdef CONFIG_SPI
125 	configure_module_pin_mux(spi0_pin_mux);
126 #endif
127 }
128