1 /* 2 * mux.c 3 * 4 * Copyright (C) 2013 Lemonage Software GmbH 5 * Author Lars Poeschel <poeschel@lemonage.de> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <common.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/hardware.h> 20 #include <asm/arch/mux.h> 21 #include <asm/io.h> 22 #include "board.h" 23 24 static struct module_pin_mux uart0_pin_mux[] = { 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 27 {-1}, 28 }; 29 30 #ifdef CONFIG_MMC 31 static struct module_pin_mux mmc0_pin_mux[] = { 32 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 33 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 34 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 35 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 36 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 37 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 38 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ 39 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 40 {-1}, 41 }; 42 #endif 43 44 #ifdef CONFIG_I2C 45 static struct module_pin_mux i2c0_pin_mux[] = { 46 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 47 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 48 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 49 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 50 {-1}, 51 }; 52 #endif 53 54 #ifdef CONFIG_SPI 55 static struct module_pin_mux spi0_pin_mux[] = { 56 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ 57 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | 58 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ 59 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ 60 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | 61 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ 62 {-1}, 63 }; 64 #endif 65 66 static struct module_pin_mux rmii1_pin_mux[] = { 67 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */ 68 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ 69 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ 70 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ 71 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ 72 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ 73 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ 74 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 75 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 76 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ 77 {-1}, 78 }; 79 80 static struct module_pin_mux cbmux_pin_mux[] = { 81 {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */ 82 {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */ 83 {-1}, 84 }; 85 86 #ifdef CONFIG_NAND 87 static struct module_pin_mux nand_pin_mux[] = { 88 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 89 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 90 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 91 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 92 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 93 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 94 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 95 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 96 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 97 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 98 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 99 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 100 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 101 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 102 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 103 {-1}, 104 }; 105 #endif 106 107 void enable_uart0_pin_mux(void) 108 { 109 configure_module_pin_mux(uart0_pin_mux); 110 } 111 112 void enable_i2c0_pin_mux(void) 113 { 114 configure_module_pin_mux(i2c0_pin_mux); 115 } 116 117 void enable_board_pin_mux() 118 { 119 configure_module_pin_mux(rmii1_pin_mux); 120 configure_module_pin_mux(mmc0_pin_mux); 121 configure_module_pin_mux(cbmux_pin_mux); 122 #ifdef CONFIG_NAND 123 configure_module_pin_mux(nand_pin_mux); 124 #endif 125 #ifdef CONFIG_SPI 126 configure_module_pin_mux(spi0_pin_mux); 127 #endif 128 } 129