1 /* 2 * board.c 3 * 4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards 5 * 6 * Copyright (C) 2013 Lemonage Software GmbH 7 * Author Lars Poeschel <poeschel@lemonage.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <spl.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/mmc_host_def.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <cpsw.h> 29 #include "board.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* MII mode defines */ 34 #define RMII_RGMII2_MODE_ENABLE 0x49 35 36 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 37 38 #ifdef CONFIG_SPL_BUILD 39 40 /* DDR RAM defines */ 41 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ 42 43 #define OSC (V_OSCK/1000000) 44 const struct dpll_params dpll_ddr = { 45 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1}; 46 47 const struct dpll_params *get_dpll_ddr_params(void) 48 { 49 return &dpll_ddr; 50 } 51 52 static const struct ddr_data ddr3_data = { 53 .datardsratio0 = MT41J256M8HX15E_RD_DQS, 54 .datawdsratio0 = MT41J256M8HX15E_WR_DQS, 55 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, 56 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, 57 .datadldiff0 = PHY_DLL_LOCK_DIFF, 58 }; 59 60 static const struct cmd_control ddr3_cmd_ctrl_data = { 61 .cmd0csratio = MT41J256M8HX15E_RATIO, 62 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 63 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 64 65 .cmd1csratio = MT41J256M8HX15E_RATIO, 66 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 67 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 68 69 .cmd2csratio = MT41J256M8HX15E_RATIO, 70 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 71 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 72 }; 73 74 static struct emif_regs ddr3_emif_reg_data = { 75 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG, 76 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF, 77 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1, 78 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, 79 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, 80 .zq_config = MT41J256M8HX15E_ZQ_CFG, 81 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | 82 PHY_EN_DYN_PWRDN, 83 }; 84 85 void set_uart_mux_conf(void) 86 { 87 enable_uart0_pin_mux(); 88 } 89 90 void set_mux_conf_regs(void) 91 { 92 /* Initalize the board header */ 93 enable_i2c0_pin_mux(); 94 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 95 96 enable_board_pin_mux(); 97 } 98 99 void sdram_init(void) 100 { 101 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, 102 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 103 } 104 #endif 105 106 /* 107 * Basic board specific setup. Pinmux has been handled already. 108 */ 109 int board_init(void) 110 { 111 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 112 113 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 114 115 return 0; 116 } 117 118 #ifdef CONFIG_DRIVER_TI_CPSW 119 static void cpsw_control(int enabled) 120 { 121 /* VTP can be added here */ 122 123 return; 124 } 125 126 static struct cpsw_slave_data cpsw_slaves[] = { 127 { 128 .slave_reg_ofs = 0x208, 129 .sliver_reg_ofs = 0xd80, 130 .phy_id = 0, 131 .phy_if = PHY_INTERFACE_MODE_RGMII, 132 }, 133 { 134 .slave_reg_ofs = 0x308, 135 .sliver_reg_ofs = 0xdc0, 136 .phy_id = 1, 137 .phy_if = PHY_INTERFACE_MODE_RGMII, 138 }, 139 }; 140 141 static struct cpsw_platform_data cpsw_data = { 142 .mdio_base = CPSW_MDIO_BASE, 143 .cpsw_base = CPSW_BASE, 144 .mdio_div = 0xff, 145 .channels = 8, 146 .cpdma_reg_ofs = 0x800, 147 .slaves = 1, 148 .slave_data = cpsw_slaves, 149 .ale_reg_ofs = 0xd00, 150 .ale_entries = 1024, 151 .host_port_reg_ofs = 0x108, 152 .hw_stats_reg_ofs = 0x900, 153 .bd_ram_ofs = 0x2000, 154 .mac_control = (1 << 5), 155 .control = cpsw_control, 156 .host_port_num = 0, 157 .version = CPSW_CTRL_VERSION_2, 158 }; 159 #endif 160 161 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 162 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 163 int board_eth_init(bd_t *bis) 164 { 165 int rv, n = 0; 166 #ifdef CONFIG_DRIVER_TI_CPSW 167 uint8_t mac_addr[6]; 168 uint32_t mac_hi, mac_lo; 169 170 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 171 printf("<ethaddr> not set. Reading from E-fuse\n"); 172 /* try reading mac address from efuse */ 173 mac_lo = readl(&cdev->macid0l); 174 mac_hi = readl(&cdev->macid0h); 175 mac_addr[0] = mac_hi & 0xFF; 176 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 177 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 178 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 179 mac_addr[4] = mac_lo & 0xFF; 180 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 181 182 if (is_valid_ether_addr(mac_addr)) 183 eth_setenv_enetaddr("ethaddr", mac_addr); 184 else 185 goto try_usbether; 186 } 187 188 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); 189 190 rv = cpsw_register(&cpsw_data); 191 if (rv < 0) 192 printf("Error %d registering CPSW switch\n", rv); 193 else 194 n += rv; 195 try_usbether: 196 #endif 197 198 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) 199 rv = usb_eth_initialize(bis); 200 if (rv < 0) 201 printf("Error %d registering USB_ETHER\n", rv); 202 else 203 n += rv; 204 #endif 205 return n; 206 } 207 #endif 208