1 /* 2 * board.c 3 * 4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards 5 * 6 * Copyright (C) 2013 Lemonage Software GmbH 7 * Author Lars Poeschel <poeschel@lemonage.de> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <common.h> 21 #include <errno.h> 22 #include <spl.h> 23 #include <asm/arch/cpu.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/omap.h> 26 #include <asm/arch/ddr_defs.h> 27 #include <asm/arch/clock.h> 28 #include <asm/arch/gpio.h> 29 #include <asm/arch/mmc_host_def.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/io.h> 32 #include <asm/emif.h> 33 #include <asm/gpio.h> 34 #include <i2c.h> 35 #include <miiphy.h> 36 #include <cpsw.h> 37 #include "board.h" 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 42 #ifdef CONFIG_SPL_BUILD 43 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 44 #endif 45 46 /* MII mode defines */ 47 #define MII_MODE_ENABLE 0x0 48 #define RGMII_MODE_ENABLE 0xA 49 #define RMII_RGMII2_MODE_ENABLE 0x49 50 51 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 52 53 /* UART defines */ 54 #ifdef CONFIG_SPL_BUILD 55 #define UART_RESET (0x1 << 1) 56 #define UART_CLK_RUNNING_MASK 0x1 57 #define UART_SMART_IDLE_EN (0x1 << 0x3) 58 59 /* DDR RAM defines */ 60 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ 61 62 static void rtc32k_enable(void) 63 { 64 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; 65 66 /* 67 * Unlock the RTC's registers. For more details please see the 68 * RTC_SS section of the TRM. In order to unlock we need to 69 * write these specific values (keys) in this order. 70 */ 71 writel(0x83e70b13, &rtc->kick0r); 72 writel(0x95a4f1e0, &rtc->kick1r); 73 74 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 75 writel((1 << 3) | (1 << 6), &rtc->osc); 76 } 77 78 static const struct ddr_data ddr3_data = { 79 .datardsratio0 = MT41J256M8HX15E_RD_DQS, 80 .datawdsratio0 = MT41J256M8HX15E_WR_DQS, 81 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, 82 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, 83 .datadldiff0 = PHY_DLL_LOCK_DIFF, 84 }; 85 86 static const struct cmd_control ddr3_cmd_ctrl_data = { 87 .cmd0csratio = MT41J256M8HX15E_RATIO, 88 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 89 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 90 91 .cmd1csratio = MT41J256M8HX15E_RATIO, 92 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 93 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 94 95 .cmd2csratio = MT41J256M8HX15E_RATIO, 96 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 97 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 98 }; 99 100 static struct emif_regs ddr3_emif_reg_data = { 101 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG, 102 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF, 103 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1, 104 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, 105 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, 106 .zq_config = MT41J256M8HX15E_ZQ_CFG, 107 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | 108 PHY_EN_DYN_PWRDN, 109 }; 110 #endif 111 112 /* 113 * early system init of muxing and clocks. 114 */ 115 void s_init(void) 116 { 117 /* 118 * Save the boot parameters passed from romcode. 119 * We cannot delay the saving further than this, 120 * to prevent overwrites. 121 */ 122 #ifdef CONFIG_SPL_BUILD 123 save_omap_boot_params(); 124 #endif 125 126 /* 127 * WDT1 is already running when the bootloader gets control 128 * Disable it to avoid "random" resets 129 */ 130 writel(0xAAAA, &wdtimer->wdtwspr); 131 while (readl(&wdtimer->wdtwwps) != 0x0) 132 ; 133 writel(0x5555, &wdtimer->wdtwspr); 134 while (readl(&wdtimer->wdtwwps) != 0x0) 135 ; 136 137 #ifdef CONFIG_SPL_BUILD 138 /* Setup the PLLs and the clocks for the peripherals */ 139 pll_init(); 140 141 /* Enable RTC32K clock */ 142 rtc32k_enable(); 143 144 /* UART softreset */ 145 u32 regval; 146 147 enable_uart0_pin_mux(); 148 149 regval = readl(&uart_base->uartsyscfg); 150 regval |= UART_RESET; 151 writel(regval, &uart_base->uartsyscfg); 152 while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK) 153 != UART_CLK_RUNNING_MASK) 154 ; 155 156 /* Disable smart idle */ 157 regval = readl(&uart_base->uartsyscfg); 158 regval |= UART_SMART_IDLE_EN; 159 writel(regval, &uart_base->uartsyscfg); 160 161 gd = &gdata; 162 163 preloader_console_init(); 164 165 /* Initalize the board header */ 166 enable_i2c0_pin_mux(); 167 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 168 169 enable_board_pin_mux(); 170 171 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, 172 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 173 #endif 174 } 175 176 /* 177 * Basic board specific setup. Pinmux has been handled already. 178 */ 179 int board_init(void) 180 { 181 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 182 183 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 184 185 return 0; 186 } 187 188 #ifdef CONFIG_DRIVER_TI_CPSW 189 static void cpsw_control(int enabled) 190 { 191 /* VTP can be added here */ 192 193 return; 194 } 195 196 static struct cpsw_slave_data cpsw_slaves[] = { 197 { 198 .slave_reg_ofs = 0x208, 199 .sliver_reg_ofs = 0xd80, 200 .phy_id = 0, 201 .phy_if = PHY_INTERFACE_MODE_RGMII, 202 }, 203 { 204 .slave_reg_ofs = 0x308, 205 .sliver_reg_ofs = 0xdc0, 206 .phy_id = 1, 207 .phy_if = PHY_INTERFACE_MODE_RGMII, 208 }, 209 }; 210 211 static struct cpsw_platform_data cpsw_data = { 212 .mdio_base = CPSW_MDIO_BASE, 213 .cpsw_base = CPSW_BASE, 214 .mdio_div = 0xff, 215 .channels = 8, 216 .cpdma_reg_ofs = 0x800, 217 .slaves = 1, 218 .slave_data = cpsw_slaves, 219 .ale_reg_ofs = 0xd00, 220 .ale_entries = 1024, 221 .host_port_reg_ofs = 0x108, 222 .hw_stats_reg_ofs = 0x900, 223 .mac_control = (1 << 5), 224 .control = cpsw_control, 225 .host_port_num = 0, 226 .version = CPSW_CTRL_VERSION_2, 227 }; 228 #endif 229 230 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 231 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 232 int board_eth_init(bd_t *bis) 233 { 234 int rv, n = 0; 235 #ifdef CONFIG_DRIVER_TI_CPSW 236 uint8_t mac_addr[6]; 237 uint32_t mac_hi, mac_lo; 238 239 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 240 printf("<ethaddr> not set. Reading from E-fuse\n"); 241 /* try reading mac address from efuse */ 242 mac_lo = readl(&cdev->macid0l); 243 mac_hi = readl(&cdev->macid0h); 244 mac_addr[0] = mac_hi & 0xFF; 245 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 246 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 247 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 248 mac_addr[4] = mac_lo & 0xFF; 249 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 250 251 if (is_valid_ether_addr(mac_addr)) 252 eth_setenv_enetaddr("ethaddr", mac_addr); 253 else 254 goto try_usbether; 255 } 256 257 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); 258 259 rv = cpsw_register(&cpsw_data); 260 if (rv < 0) 261 printf("Error %d registering CPSW switch\n", rv); 262 else 263 n += rv; 264 try_usbether: 265 #endif 266 267 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) 268 rv = usb_eth_initialize(bis); 269 if (rv < 0) 270 printf("Error %d registering USB_ETHER\n", rv); 271 else 272 n += rv; 273 #endif 274 return n; 275 } 276 #endif 277