1 /* 2 * board.c 3 * 4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards 5 * 6 * Copyright (C) 2013 Lemonage Software GmbH 7 * Author Lars Poeschel <poeschel@lemonage.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <spl.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/mmc_host_def.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <cpsw.h> 29 #include "board.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* MII mode defines */ 34 #define RMII_RGMII2_MODE_ENABLE 0x49 35 36 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 37 38 #ifdef CONFIG_SPL_BUILD 39 40 /* DDR RAM defines */ 41 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ 42 43 #define OSC (V_OSCK/1000000) 44 const struct dpll_params dpll_ddr = { 45 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1}; 46 47 const struct dpll_params *get_dpll_ddr_params(void) 48 { 49 return &dpll_ddr; 50 } 51 52 #ifdef CONFIG_REV1 53 static const struct ddr_data ddr3_data = { 54 .datardsratio0 = MT41J256M8HX15E_RD_DQS, 55 .datawdsratio0 = MT41J256M8HX15E_WR_DQS, 56 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, 57 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, 58 }; 59 60 static const struct cmd_control ddr3_cmd_ctrl_data = { 61 .cmd0csratio = MT41J256M8HX15E_RATIO, 62 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 63 64 .cmd1csratio = MT41J256M8HX15E_RATIO, 65 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 66 67 .cmd2csratio = MT41J256M8HX15E_RATIO, 68 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 69 }; 70 71 static struct emif_regs ddr3_emif_reg_data = { 72 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG, 73 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF, 74 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1, 75 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, 76 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, 77 .zq_config = MT41J256M8HX15E_ZQ_CFG, 78 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | 79 PHY_EN_DYN_PWRDN, 80 }; 81 82 void sdram_init(void) 83 { 84 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, 85 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 86 } 87 #else 88 static const struct ddr_data ddr3_data = { 89 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 90 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 91 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 92 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 93 }; 94 95 static const struct cmd_control ddr3_cmd_ctrl_data = { 96 .cmd0csratio = MT41K256M16HA125E_RATIO, 97 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 98 99 .cmd1csratio = MT41K256M16HA125E_RATIO, 100 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 101 102 .cmd2csratio = MT41K256M16HA125E_RATIO, 103 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 104 }; 105 106 static struct emif_regs ddr3_emif_reg_data = { 107 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 108 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 109 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 110 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 111 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 112 .zq_config = MT41K256M16HA125E_ZQ_CFG, 113 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | 114 PHY_EN_DYN_PWRDN, 115 }; 116 117 void sdram_init(void) 118 { 119 config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data, 120 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 121 } 122 #endif 123 124 void set_uart_mux_conf(void) 125 { 126 enable_uart0_pin_mux(); 127 } 128 129 void set_mux_conf_regs(void) 130 { 131 /* Initalize the board header */ 132 enable_i2c0_pin_mux(); 133 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 134 135 enable_board_pin_mux(); 136 } 137 #endif 138 139 /* 140 * Basic board specific setup. Pinmux has been handled already. 141 */ 142 int board_init(void) 143 { 144 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 145 146 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 147 148 return 0; 149 } 150 151 #ifdef CONFIG_DRIVER_TI_CPSW 152 static void cpsw_control(int enabled) 153 { 154 /* VTP can be added here */ 155 156 return; 157 } 158 159 static struct cpsw_slave_data cpsw_slaves[] = { 160 { 161 .slave_reg_ofs = 0x208, 162 .sliver_reg_ofs = 0xd80, 163 .phy_id = 0, 164 .phy_if = PHY_INTERFACE_MODE_RGMII, 165 }, 166 { 167 .slave_reg_ofs = 0x308, 168 .sliver_reg_ofs = 0xdc0, 169 .phy_id = 1, 170 .phy_if = PHY_INTERFACE_MODE_RGMII, 171 }, 172 }; 173 174 static struct cpsw_platform_data cpsw_data = { 175 .mdio_base = CPSW_MDIO_BASE, 176 .cpsw_base = CPSW_BASE, 177 .mdio_div = 0xff, 178 .channels = 8, 179 .cpdma_reg_ofs = 0x800, 180 .slaves = 1, 181 .slave_data = cpsw_slaves, 182 .ale_reg_ofs = 0xd00, 183 .ale_entries = 1024, 184 .host_port_reg_ofs = 0x108, 185 .hw_stats_reg_ofs = 0x900, 186 .bd_ram_ofs = 0x2000, 187 .mac_control = (1 << 5), 188 .control = cpsw_control, 189 .host_port_num = 0, 190 .version = CPSW_CTRL_VERSION_2, 191 }; 192 #endif 193 194 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 195 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 196 int board_eth_init(bd_t *bis) 197 { 198 int rv, n = 0; 199 #ifdef CONFIG_DRIVER_TI_CPSW 200 uint8_t mac_addr[6]; 201 uint32_t mac_hi, mac_lo; 202 203 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 204 printf("<ethaddr> not set. Reading from E-fuse\n"); 205 /* try reading mac address from efuse */ 206 mac_lo = readl(&cdev->macid0l); 207 mac_hi = readl(&cdev->macid0h); 208 mac_addr[0] = mac_hi & 0xFF; 209 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 210 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 211 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 212 mac_addr[4] = mac_lo & 0xFF; 213 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 214 215 if (is_valid_ether_addr(mac_addr)) 216 eth_setenv_enetaddr("ethaddr", mac_addr); 217 else 218 goto try_usbether; 219 } 220 221 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); 222 223 rv = cpsw_register(&cpsw_data); 224 if (rv < 0) 225 printf("Error %d registering CPSW switch\n", rv); 226 else 227 n += rv; 228 try_usbether: 229 #endif 230 231 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) 232 rv = usb_eth_initialize(bis); 233 if (rv < 0) 234 printf("Error %d registering USB_ETHER\n", rv); 235 else 236 n += rv; 237 #endif 238 return n; 239 } 240 #endif 241