1 /* 2 * board.c 3 * 4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards 5 * 6 * Copyright (C) 2013 Lemonage Software GmbH 7 * Author Lars Poeschel <poeschel@lemonage.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <spl.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/mmc_host_def.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <cpsw.h> 29 #include "board.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 34 35 /* MII mode defines */ 36 #define MII_MODE_ENABLE 0x0 37 #define RGMII_MODE_ENABLE 0xA 38 #define RMII_RGMII2_MODE_ENABLE 0x49 39 40 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 41 42 #ifdef CONFIG_SPL_BUILD 43 44 /* DDR RAM defines */ 45 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ 46 47 static const struct ddr_data ddr3_data = { 48 .datardsratio0 = MT41J256M8HX15E_RD_DQS, 49 .datawdsratio0 = MT41J256M8HX15E_WR_DQS, 50 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, 51 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, 52 .datadldiff0 = PHY_DLL_LOCK_DIFF, 53 }; 54 55 static const struct cmd_control ddr3_cmd_ctrl_data = { 56 .cmd0csratio = MT41J256M8HX15E_RATIO, 57 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 58 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 59 60 .cmd1csratio = MT41J256M8HX15E_RATIO, 61 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 62 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 63 64 .cmd2csratio = MT41J256M8HX15E_RATIO, 65 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 66 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 67 }; 68 69 static struct emif_regs ddr3_emif_reg_data = { 70 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG, 71 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF, 72 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1, 73 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, 74 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, 75 .zq_config = MT41J256M8HX15E_ZQ_CFG, 76 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | 77 PHY_EN_DYN_PWRDN, 78 }; 79 #endif 80 81 /* 82 * early system init of muxing and clocks. 83 */ 84 void s_init(void) 85 { 86 /* 87 * Save the boot parameters passed from romcode. 88 * We cannot delay the saving further than this, 89 * to prevent overwrites. 90 */ 91 #ifdef CONFIG_SPL_BUILD 92 save_omap_boot_params(); 93 #endif 94 95 /* 96 * WDT1 is already running when the bootloader gets control 97 * Disable it to avoid "random" resets 98 */ 99 writel(0xAAAA, &wdtimer->wdtwspr); 100 while (readl(&wdtimer->wdtwwps) != 0x0) 101 ; 102 writel(0x5555, &wdtimer->wdtwspr); 103 while (readl(&wdtimer->wdtwwps) != 0x0) 104 ; 105 106 #ifdef CONFIG_SPL_BUILD 107 /* Setup the PLLs and the clocks for the peripherals */ 108 pll_init(); 109 110 /* Enable RTC32K clock */ 111 rtc32k_enable(); 112 113 enable_uart0_pin_mux(); 114 uart_soft_reset(); 115 116 gd = &gdata; 117 118 preloader_console_init(); 119 120 /* Initalize the board header */ 121 enable_i2c0_pin_mux(); 122 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 123 124 enable_board_pin_mux(); 125 126 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, 127 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 128 #endif 129 } 130 131 /* 132 * Basic board specific setup. Pinmux has been handled already. 133 */ 134 int board_init(void) 135 { 136 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 137 138 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 139 140 return 0; 141 } 142 143 #ifdef CONFIG_DRIVER_TI_CPSW 144 static void cpsw_control(int enabled) 145 { 146 /* VTP can be added here */ 147 148 return; 149 } 150 151 static struct cpsw_slave_data cpsw_slaves[] = { 152 { 153 .slave_reg_ofs = 0x208, 154 .sliver_reg_ofs = 0xd80, 155 .phy_id = 0, 156 .phy_if = PHY_INTERFACE_MODE_RGMII, 157 }, 158 { 159 .slave_reg_ofs = 0x308, 160 .sliver_reg_ofs = 0xdc0, 161 .phy_id = 1, 162 .phy_if = PHY_INTERFACE_MODE_RGMII, 163 }, 164 }; 165 166 static struct cpsw_platform_data cpsw_data = { 167 .mdio_base = CPSW_MDIO_BASE, 168 .cpsw_base = CPSW_BASE, 169 .mdio_div = 0xff, 170 .channels = 8, 171 .cpdma_reg_ofs = 0x800, 172 .slaves = 1, 173 .slave_data = cpsw_slaves, 174 .ale_reg_ofs = 0xd00, 175 .ale_entries = 1024, 176 .host_port_reg_ofs = 0x108, 177 .hw_stats_reg_ofs = 0x900, 178 .mac_control = (1 << 5), 179 .control = cpsw_control, 180 .host_port_num = 0, 181 .version = CPSW_CTRL_VERSION_2, 182 }; 183 #endif 184 185 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 186 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 187 int board_eth_init(bd_t *bis) 188 { 189 int rv, n = 0; 190 #ifdef CONFIG_DRIVER_TI_CPSW 191 uint8_t mac_addr[6]; 192 uint32_t mac_hi, mac_lo; 193 194 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 195 printf("<ethaddr> not set. Reading from E-fuse\n"); 196 /* try reading mac address from efuse */ 197 mac_lo = readl(&cdev->macid0l); 198 mac_hi = readl(&cdev->macid0h); 199 mac_addr[0] = mac_hi & 0xFF; 200 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 201 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 202 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 203 mac_addr[4] = mac_lo & 0xFF; 204 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 205 206 if (is_valid_ether_addr(mac_addr)) 207 eth_setenv_enetaddr("ethaddr", mac_addr); 208 else 209 goto try_usbether; 210 } 211 212 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); 213 214 rv = cpsw_register(&cpsw_data); 215 if (rv < 0) 216 printf("Error %d registering CPSW switch\n", rv); 217 else 218 n += rv; 219 try_usbether: 220 #endif 221 222 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) 223 rv = usb_eth_initialize(bis); 224 if (rv < 0) 225 printf("Error %d registering USB_ETHER\n", rv); 226 else 227 n += rv; 228 #endif 229 return n; 230 } 231 #endif 232