1 /* 2 * board.c 3 * 4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards 5 * 6 * Copyright (C) 2013 Lemonage Software GmbH 7 * Author Lars Poeschel <poeschel@lemonage.de> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <common.h> 21 #include <errno.h> 22 #include <spl.h> 23 #include <asm/arch/cpu.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/omap.h> 26 #include <asm/arch/ddr_defs.h> 27 #include <asm/arch/clock.h> 28 #include <asm/arch/gpio.h> 29 #include <asm/arch/mmc_host_def.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/io.h> 32 #include <asm/emif.h> 33 #include <asm/gpio.h> 34 #include <i2c.h> 35 #include <miiphy.h> 36 #include <cpsw.h> 37 #include "board.h" 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 42 43 /* MII mode defines */ 44 #define MII_MODE_ENABLE 0x0 45 #define RGMII_MODE_ENABLE 0xA 46 #define RMII_RGMII2_MODE_ENABLE 0x49 47 48 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 49 50 #ifdef CONFIG_SPL_BUILD 51 52 /* DDR RAM defines */ 53 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ 54 55 static const struct ddr_data ddr3_data = { 56 .datardsratio0 = MT41J256M8HX15E_RD_DQS, 57 .datawdsratio0 = MT41J256M8HX15E_WR_DQS, 58 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, 59 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, 60 .datadldiff0 = PHY_DLL_LOCK_DIFF, 61 }; 62 63 static const struct cmd_control ddr3_cmd_ctrl_data = { 64 .cmd0csratio = MT41J256M8HX15E_RATIO, 65 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 66 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 67 68 .cmd1csratio = MT41J256M8HX15E_RATIO, 69 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 70 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 71 72 .cmd2csratio = MT41J256M8HX15E_RATIO, 73 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, 74 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, 75 }; 76 77 static struct emif_regs ddr3_emif_reg_data = { 78 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG, 79 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF, 80 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1, 81 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, 82 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, 83 .zq_config = MT41J256M8HX15E_ZQ_CFG, 84 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | 85 PHY_EN_DYN_PWRDN, 86 }; 87 #endif 88 89 /* 90 * early system init of muxing and clocks. 91 */ 92 void s_init(void) 93 { 94 /* 95 * Save the boot parameters passed from romcode. 96 * We cannot delay the saving further than this, 97 * to prevent overwrites. 98 */ 99 #ifdef CONFIG_SPL_BUILD 100 save_omap_boot_params(); 101 #endif 102 103 /* 104 * WDT1 is already running when the bootloader gets control 105 * Disable it to avoid "random" resets 106 */ 107 writel(0xAAAA, &wdtimer->wdtwspr); 108 while (readl(&wdtimer->wdtwwps) != 0x0) 109 ; 110 writel(0x5555, &wdtimer->wdtwspr); 111 while (readl(&wdtimer->wdtwwps) != 0x0) 112 ; 113 114 #ifdef CONFIG_SPL_BUILD 115 /* Setup the PLLs and the clocks for the peripherals */ 116 pll_init(); 117 118 /* Enable RTC32K clock */ 119 rtc32k_enable(); 120 121 enable_uart0_pin_mux(); 122 uart_soft_reset(); 123 124 gd = &gdata; 125 126 preloader_console_init(); 127 128 /* Initalize the board header */ 129 enable_i2c0_pin_mux(); 130 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 131 132 enable_board_pin_mux(); 133 134 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, 135 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 136 #endif 137 } 138 139 /* 140 * Basic board specific setup. Pinmux has been handled already. 141 */ 142 int board_init(void) 143 { 144 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 145 146 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 147 148 return 0; 149 } 150 151 #ifdef CONFIG_DRIVER_TI_CPSW 152 static void cpsw_control(int enabled) 153 { 154 /* VTP can be added here */ 155 156 return; 157 } 158 159 static struct cpsw_slave_data cpsw_slaves[] = { 160 { 161 .slave_reg_ofs = 0x208, 162 .sliver_reg_ofs = 0xd80, 163 .phy_id = 0, 164 .phy_if = PHY_INTERFACE_MODE_RGMII, 165 }, 166 { 167 .slave_reg_ofs = 0x308, 168 .sliver_reg_ofs = 0xdc0, 169 .phy_id = 1, 170 .phy_if = PHY_INTERFACE_MODE_RGMII, 171 }, 172 }; 173 174 static struct cpsw_platform_data cpsw_data = { 175 .mdio_base = CPSW_MDIO_BASE, 176 .cpsw_base = CPSW_BASE, 177 .mdio_div = 0xff, 178 .channels = 8, 179 .cpdma_reg_ofs = 0x800, 180 .slaves = 1, 181 .slave_data = cpsw_slaves, 182 .ale_reg_ofs = 0xd00, 183 .ale_entries = 1024, 184 .host_port_reg_ofs = 0x108, 185 .hw_stats_reg_ofs = 0x900, 186 .mac_control = (1 << 5), 187 .control = cpsw_control, 188 .host_port_num = 0, 189 .version = CPSW_CTRL_VERSION_2, 190 }; 191 #endif 192 193 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 194 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 195 int board_eth_init(bd_t *bis) 196 { 197 int rv, n = 0; 198 #ifdef CONFIG_DRIVER_TI_CPSW 199 uint8_t mac_addr[6]; 200 uint32_t mac_hi, mac_lo; 201 202 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 203 printf("<ethaddr> not set. Reading from E-fuse\n"); 204 /* try reading mac address from efuse */ 205 mac_lo = readl(&cdev->macid0l); 206 mac_hi = readl(&cdev->macid0h); 207 mac_addr[0] = mac_hi & 0xFF; 208 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 209 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 210 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 211 mac_addr[4] = mac_lo & 0xFF; 212 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 213 214 if (is_valid_ether_addr(mac_addr)) 215 eth_setenv_enetaddr("ethaddr", mac_addr); 216 else 217 goto try_usbether; 218 } 219 220 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); 221 222 rv = cpsw_register(&cpsw_data); 223 if (rv < 0) 224 printf("Error %d registering CPSW switch\n", rv); 225 else 226 n += rv; 227 try_usbether: 228 #endif 229 230 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) 231 rv = usb_eth_initialize(bis); 232 if (rv < 0) 233 printf("Error %d registering USB_ETHER\n", rv); 234 else 235 n += rv; 236 #endif 237 return n; 238 } 239 #endif 240