1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maintainer : Steve Sakoman <steve@sakoman.com> 4 * 5 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Syed Mohammed Khasim <khasim@ti.com> 8 * Sunil Kumar <sunilsaini05@gmail.com> 9 * Shashi Ranjan <shashiranjanmca05@gmail.com> 10 * 11 * (C) Copyright 2004-2008 12 * Texas Instruments, <www.ti.com> 13 */ 14 #include <asm/io.h> 15 #include <asm/arch/mem.h> 16 #include <asm/arch/sys_proto.h> 17 #include "overo.h" 18 19 /* 20 * Routine: get_board_mem_timings 21 * Description: If we use SPL then there is no x-loader nor config header 22 * so we have to setup the DDR timings ourself on both banks. 23 */ 24 void get_board_mem_timings(struct board_sdrc_timings *timings) 25 { 26 timings->mr = MICRON_V_MR_165; 27 switch (get_board_revision()) { 28 case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ 29 timings->mcfg = MICRON_V_MCFG_165(256 << 20); 30 timings->ctrla = MICRON_V_ACTIMA_165; 31 timings->ctrlb = MICRON_V_ACTIMB_165; 32 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 33 break; 34 case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ 35 case REVISION_4: 36 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 37 timings->ctrla = MICRON_V_ACTIMA_200; 38 timings->ctrlb = MICRON_V_ACTIMB_200; 39 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 40 break; 41 case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ 42 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 43 timings->ctrla = HYNIX_V_ACTIMA_200; 44 timings->ctrlb = HYNIX_V_ACTIMB_200; 45 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 46 break; 47 case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ 48 timings->mcfg = MCFG(512 << 20, 15); 49 timings->ctrla = MICRON_V_ACTIMA_200; 50 timings->ctrlb = MICRON_V_ACTIMB_200; 51 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 52 break; 53 default: 54 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 55 timings->ctrla = MICRON_V_ACTIMA_165; 56 timings->ctrlb = MICRON_V_ACTIMB_165; 57 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 58 } 59 } 60