1*fe5d488fSArun Bharadwaj /* 2*fe5d488fSArun Bharadwaj * Maintainer : Steve Sakoman <steve@sakoman.com> 3*fe5d488fSArun Bharadwaj * 4*fe5d488fSArun Bharadwaj * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by 5*fe5d488fSArun Bharadwaj * Richard Woodruff <r-woodruff2@ti.com> 6*fe5d488fSArun Bharadwaj * Syed Mohammed Khasim <khasim@ti.com> 7*fe5d488fSArun Bharadwaj * Sunil Kumar <sunilsaini05@gmail.com> 8*fe5d488fSArun Bharadwaj * Shashi Ranjan <shashiranjanmca05@gmail.com> 9*fe5d488fSArun Bharadwaj * 10*fe5d488fSArun Bharadwaj * (C) Copyright 2004-2008 11*fe5d488fSArun Bharadwaj * Texas Instruments, <www.ti.com> 12*fe5d488fSArun Bharadwaj * 13*fe5d488fSArun Bharadwaj * SPDX-License-Identifier: GPL-2.0+ 14*fe5d488fSArun Bharadwaj */ 15*fe5d488fSArun Bharadwaj #include <asm/io.h> 16*fe5d488fSArun Bharadwaj #include <asm/arch/mem.h> 17*fe5d488fSArun Bharadwaj #include <asm/arch/sys_proto.h> 18*fe5d488fSArun Bharadwaj #include "overo.h" 19*fe5d488fSArun Bharadwaj 20*fe5d488fSArun Bharadwaj /* 21*fe5d488fSArun Bharadwaj * Routine: get_board_mem_timings 22*fe5d488fSArun Bharadwaj * Description: If we use SPL then there is no x-loader nor config header 23*fe5d488fSArun Bharadwaj * so we have to setup the DDR timings ourself on both banks. 24*fe5d488fSArun Bharadwaj */ 25*fe5d488fSArun Bharadwaj void get_board_mem_timings(struct board_sdrc_timings *timings) 26*fe5d488fSArun Bharadwaj { 27*fe5d488fSArun Bharadwaj timings->mr = MICRON_V_MR_165; 28*fe5d488fSArun Bharadwaj switch (get_board_revision()) { 29*fe5d488fSArun Bharadwaj case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ 30*fe5d488fSArun Bharadwaj timings->mcfg = MICRON_V_MCFG_165(256 << 20); 31*fe5d488fSArun Bharadwaj timings->ctrla = MICRON_V_ACTIMA_165; 32*fe5d488fSArun Bharadwaj timings->ctrlb = MICRON_V_ACTIMB_165; 33*fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 34*fe5d488fSArun Bharadwaj break; 35*fe5d488fSArun Bharadwaj case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ 36*fe5d488fSArun Bharadwaj case REVISION_4: 37*fe5d488fSArun Bharadwaj timings->mcfg = MICRON_V_MCFG_200(256 << 20); 38*fe5d488fSArun Bharadwaj timings->ctrla = MICRON_V_ACTIMA_200; 39*fe5d488fSArun Bharadwaj timings->ctrlb = MICRON_V_ACTIMB_200; 40*fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 41*fe5d488fSArun Bharadwaj break; 42*fe5d488fSArun Bharadwaj case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ 43*fe5d488fSArun Bharadwaj timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 44*fe5d488fSArun Bharadwaj timings->ctrla = HYNIX_V_ACTIMA_200; 45*fe5d488fSArun Bharadwaj timings->ctrlb = HYNIX_V_ACTIMB_200; 46*fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 47*fe5d488fSArun Bharadwaj break; 48*fe5d488fSArun Bharadwaj case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ 49*fe5d488fSArun Bharadwaj timings->mcfg = MCFG(512 << 20, 15); 50*fe5d488fSArun Bharadwaj timings->ctrla = MICRON_V_ACTIMA_200; 51*fe5d488fSArun Bharadwaj timings->ctrlb = MICRON_V_ACTIMB_200; 52*fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 53*fe5d488fSArun Bharadwaj break; 54*fe5d488fSArun Bharadwaj default: 55*fe5d488fSArun Bharadwaj timings->mcfg = MICRON_V_MCFG_165(128 << 20); 56*fe5d488fSArun Bharadwaj timings->ctrla = MICRON_V_ACTIMA_165; 57*fe5d488fSArun Bharadwaj timings->ctrlb = MICRON_V_ACTIMB_165; 58*fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 59*fe5d488fSArun Bharadwaj } 60*fe5d488fSArun Bharadwaj } 61