1 /* 2 * Maintainer : Steve Sakoman <steve@sakoman.com> 3 * 4 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by 5 * Richard Woodruff <r-woodruff2@ti.com> 6 * Syed Mohammed Khasim <khasim@ti.com> 7 * Sunil Kumar <sunilsaini05@gmail.com> 8 * Shashi Ranjan <shashiranjanmca05@gmail.com> 9 * 10 * (C) Copyright 2004-2008 11 * Texas Instruments, <www.ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 #include <common.h> 16 #include <netdev.h> 17 #include <twl4030.h> 18 #include <linux/mtd/nand.h> 19 #include <asm/io.h> 20 #include <asm/arch/mmc_host_def.h> 21 #include <asm/arch/mux.h> 22 #include <asm/arch/mem.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/gpio.h> 25 #include <asm/mach-types.h> 26 #include "overo.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define TWL4030_I2C_BUS 0 31 #define EXPANSION_EEPROM_I2C_BUS 2 32 #define EXPANSION_EEPROM_I2C_ADDRESS 0x51 33 34 #define GUMSTIX_SUMMIT 0x01000200 35 #define GUMSTIX_TOBI 0x02000200 36 #define GUMSTIX_TOBI_DUO 0x03000200 37 #define GUMSTIX_PALO35 0x04000200 38 #define GUMSTIX_PALO43 0x05000200 39 #define GUMSTIX_CHESTNUT43 0x06000200 40 #define GUMSTIX_PINTO 0x07000200 41 #define GUMSTIX_GALLOP43 0x08000200 42 43 #define ETTUS_USRP_E 0x01000300 44 45 #define GUMSTIX_NO_EEPROM 0xffffffff 46 47 static struct { 48 unsigned int device_vendor; 49 unsigned char revision; 50 unsigned char content; 51 char fab_revision[8]; 52 char env_var[16]; 53 char env_setting[64]; 54 } expansion_config; 55 56 #if defined(CONFIG_CMD_NET) 57 static void setup_net_chip(void); 58 #endif 59 60 /* GPMC definitions for LAN9221 chips on Tobi expansion boards */ 61 static const u32 gpmc_lan_config[] = { 62 NET_LAN9221_GPMC_CONFIG1, 63 NET_LAN9221_GPMC_CONFIG2, 64 NET_LAN9221_GPMC_CONFIG3, 65 NET_LAN9221_GPMC_CONFIG4, 66 NET_LAN9221_GPMC_CONFIG5, 67 NET_LAN9221_GPMC_CONFIG6, 68 /*CONFIG7- computed as params */ 69 }; 70 71 /* 72 * Routine: board_init 73 * Description: Early hardware init. 74 */ 75 int board_init(void) 76 { 77 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 78 /* board id for Linux */ 79 gd->bd->bi_arch_number = MACH_TYPE_OVERO; 80 /* boot param addr */ 81 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 82 83 return 0; 84 } 85 86 /* 87 * Routine: get_board_revision 88 * Description: Returns the board revision 89 */ 90 int get_board_revision(void) 91 { 92 int revision; 93 94 #ifdef CONFIG_SYS_I2C_OMAP34XX 95 unsigned char data; 96 97 /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ 98 /* these boards should return a revision number of 0 */ 99 /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */ 100 i2c_set_bus_num(TWL4030_I2C_BUS); 101 data = 0x01; 102 i2c_write(0x4B, 0x29, 1, &data, 1); 103 data = 0x0c; 104 i2c_write(0x4B, 0x2b, 1, &data, 1); 105 i2c_read(0x4B, 0x2a, 1, &data, 1); 106 #endif 107 108 if (!gpio_request(112, "") && 109 !gpio_request(113, "") && 110 !gpio_request(115, "")) { 111 112 gpio_direction_input(112); 113 gpio_direction_input(113); 114 gpio_direction_input(115); 115 116 revision = gpio_get_value(115) << 2 | 117 gpio_get_value(113) << 1 | 118 gpio_get_value(112); 119 } else { 120 puts("Error: unable to acquire board revision GPIOs\n"); 121 revision = -1; 122 } 123 124 return revision; 125 } 126 127 #ifdef CONFIG_SPL_BUILD 128 /* 129 * Routine: get_board_mem_timings 130 * Description: If we use SPL then there is no x-loader nor config header 131 * so we have to setup the DDR timings ourself on both banks. 132 */ 133 void get_board_mem_timings(struct board_sdrc_timings *timings) 134 { 135 timings->mr = MICRON_V_MR_165; 136 switch (get_board_revision()) { 137 case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ 138 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 139 timings->ctrla = MICRON_V_ACTIMA_165; 140 timings->ctrlb = MICRON_V_ACTIMB_165; 141 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 142 break; 143 case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ 144 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 145 timings->ctrla = MICRON_V_ACTIMA_200; 146 timings->ctrlb = MICRON_V_ACTIMB_200; 147 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 148 break; 149 case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ 150 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 151 timings->ctrla = HYNIX_V_ACTIMA_200; 152 timings->ctrlb = HYNIX_V_ACTIMB_200; 153 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 154 break; 155 case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ 156 timings->mcfg = MCFG(512 << 20, 15); 157 timings->ctrla = MICRON_V_ACTIMA_200; 158 timings->ctrlb = MICRON_V_ACTIMB_200; 159 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 160 break; 161 default: 162 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 163 timings->ctrla = MICRON_V_ACTIMA_165; 164 timings->ctrlb = MICRON_V_ACTIMB_165; 165 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 166 } 167 } 168 #endif 169 170 /* 171 * Routine: get_sdio2_config 172 * Description: Return information about the wifi module connection 173 * Returns 0 if the module connects though a level translator 174 * Returns 1 if the module connects directly 175 */ 176 int get_sdio2_config(void) 177 { 178 int sdio_direct; 179 180 if (!gpio_request(130, "") && !gpio_request(139, "")) { 181 182 gpio_direction_output(130, 0); 183 gpio_direction_input(139); 184 185 sdio_direct = 1; 186 gpio_set_value(130, 0); 187 if (gpio_get_value(139) == 0) { 188 gpio_set_value(130, 1); 189 if (gpio_get_value(139) == 1) 190 sdio_direct = 0; 191 } 192 193 gpio_direction_input(130); 194 } else { 195 puts("Error: unable to acquire sdio2 clk GPIOs\n"); 196 sdio_direct = -1; 197 } 198 199 return sdio_direct; 200 } 201 202 /* 203 * Routine: get_expansion_id 204 * Description: This function checks for expansion board by checking I2C 205 * bus 2 for the availability of an AT24C01B serial EEPROM. 206 * returns the device_vendor field from the EEPROM 207 */ 208 unsigned int get_expansion_id(void) 209 { 210 i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); 211 212 /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */ 213 if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) { 214 i2c_set_bus_num(TWL4030_I2C_BUS); 215 return GUMSTIX_NO_EEPROM; 216 } 217 218 /* read configuration data */ 219 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, 220 sizeof(expansion_config)); 221 222 i2c_set_bus_num(TWL4030_I2C_BUS); 223 224 return expansion_config.device_vendor; 225 } 226 227 /* 228 * Routine: misc_init_r 229 * Description: Configure board specific parts 230 */ 231 int misc_init_r(void) 232 { 233 twl4030_power_init(); 234 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 235 236 #if defined(CONFIG_CMD_NET) 237 setup_net_chip(); 238 #endif 239 240 printf("Board revision: %d\n", get_board_revision()); 241 242 switch (get_sdio2_config()) { 243 case 0: 244 puts("Tranceiver detected on mmc2\n"); 245 MUX_OVERO_SDIO2_TRANSCEIVER(); 246 break; 247 case 1: 248 puts("Direct connection on mmc2\n"); 249 MUX_OVERO_SDIO2_DIRECT(); 250 break; 251 default: 252 puts("Unable to detect mmc2 connection type\n"); 253 } 254 255 switch (get_expansion_id()) { 256 case GUMSTIX_SUMMIT: 257 printf("Recognized Summit expansion board (rev %d %s)\n", 258 expansion_config.revision, 259 expansion_config.fab_revision); 260 setenv("defaultdisplay", "dvi"); 261 break; 262 case GUMSTIX_TOBI: 263 printf("Recognized Tobi expansion board (rev %d %s)\n", 264 expansion_config.revision, 265 expansion_config.fab_revision); 266 setenv("defaultdisplay", "dvi"); 267 break; 268 case GUMSTIX_TOBI_DUO: 269 printf("Recognized Tobi Duo expansion board (rev %d %s)\n", 270 expansion_config.revision, 271 expansion_config.fab_revision); 272 /* second lan chip */ 273 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 274 0x2B000000, GPMC_SIZE_16M); 275 break; 276 case GUMSTIX_PALO35: 277 printf("Recognized Palo35 expansion board (rev %d %s)\n", 278 expansion_config.revision, 279 expansion_config.fab_revision); 280 setenv("defaultdisplay", "lcd35"); 281 break; 282 case GUMSTIX_PALO43: 283 printf("Recognized Palo43 expansion board (rev %d %s)\n", 284 expansion_config.revision, 285 expansion_config.fab_revision); 286 setenv("defaultdisplay", "lcd43"); 287 break; 288 case GUMSTIX_CHESTNUT43: 289 printf("Recognized Chestnut43 expansion board (rev %d %s)\n", 290 expansion_config.revision, 291 expansion_config.fab_revision); 292 setenv("defaultdisplay", "lcd43"); 293 break; 294 case GUMSTIX_PINTO: 295 printf("Recognized Pinto expansion board (rev %d %s)\n", 296 expansion_config.revision, 297 expansion_config.fab_revision); 298 break; 299 case GUMSTIX_GALLOP43: 300 printf("Recognized Gallop43 expansion board (rev %d %s)\n", 301 expansion_config.revision, 302 expansion_config.fab_revision); 303 setenv("defaultdisplay", "lcd43"); 304 break; 305 case ETTUS_USRP_E: 306 printf("Recognized Ettus Research USRP-E (rev %d %s)\n", 307 expansion_config.revision, 308 expansion_config.fab_revision); 309 MUX_USRP_E(); 310 setenv("defaultdisplay", "dvi"); 311 break; 312 case GUMSTIX_NO_EEPROM: 313 puts("No EEPROM on expansion board\n"); 314 break; 315 default: 316 puts("Unrecognized expansion board\n"); 317 } 318 319 if (expansion_config.content == 1) 320 setenv(expansion_config.env_var, expansion_config.env_setting); 321 322 dieid_num_r(); 323 324 return 0; 325 } 326 327 /* 328 * Routine: set_muxconf_regs 329 * Description: Setting up the configuration Mux registers specific to the 330 * hardware. Many pins need to be moved from protect to primary 331 * mode. 332 */ 333 void set_muxconf_regs(void) 334 { 335 MUX_OVERO(); 336 } 337 338 #if defined(CONFIG_CMD_NET) 339 /* 340 * Routine: setup_net_chip 341 * Description: Setting up the configuration GPMC registers specific to the 342 * Ethernet hardware. 343 */ 344 static void setup_net_chip(void) 345 { 346 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 347 348 /* first lan chip */ 349 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 350 GPMC_SIZE_16M); 351 352 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 353 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 354 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 355 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 356 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 357 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 358 &ctrl_base->gpmc_nadv_ale); 359 360 /* Make GPIO 64 as output pin and send a magic pulse through it */ 361 if (!gpio_request(64, "")) { 362 gpio_direction_output(64, 0); 363 gpio_set_value(64, 1); 364 udelay(1); 365 gpio_set_value(64, 0); 366 udelay(1); 367 gpio_set_value(64, 1); 368 } 369 } 370 #endif 371 372 int board_eth_init(bd_t *bis) 373 { 374 int rc = 0; 375 #ifdef CONFIG_SMC911X 376 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 377 #endif 378 return rc; 379 } 380 381 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 382 int board_mmc_init(bd_t *bis) 383 { 384 return omap_mmc_init(0, 0, 0, -1, -1); 385 } 386 #endif 387