1 /* 2 * Maintainer : Steve Sakoman <steve@sakoman.com> 3 * 4 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by 5 * Richard Woodruff <r-woodruff2@ti.com> 6 * Syed Mohammed Khasim <khasim@ti.com> 7 * Sunil Kumar <sunilsaini05@gmail.com> 8 * Shashi Ranjan <shashiranjanmca05@gmail.com> 9 * 10 * (C) Copyright 2004-2008 11 * Texas Instruments, <www.ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 #include <common.h> 16 #include <netdev.h> 17 #include <twl4030.h> 18 #include <linux/mtd/nand.h> 19 #include <asm/io.h> 20 #include <asm/arch/mmc_host_def.h> 21 #include <asm/arch/mux.h> 22 #include <asm/arch/mem.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/omap_gpmc.h> 25 #include <asm/gpio.h> 26 #include <asm/mach-types.h> 27 #include "overo.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define TWL4030_I2C_BUS 0 32 #define EXPANSION_EEPROM_I2C_BUS 2 33 #define EXPANSION_EEPROM_I2C_ADDRESS 0x51 34 35 #define GUMSTIX_SUMMIT 0x01000200 36 #define GUMSTIX_TOBI 0x02000200 37 #define GUMSTIX_TOBI_DUO 0x03000200 38 #define GUMSTIX_PALO35 0x04000200 39 #define GUMSTIX_PALO43 0x05000200 40 #define GUMSTIX_CHESTNUT43 0x06000200 41 #define GUMSTIX_PINTO 0x07000200 42 #define GUMSTIX_GALLOP43 0x08000200 43 44 #define ETTUS_USRP_E 0x01000300 45 46 #define GUMSTIX_NO_EEPROM 0xffffffff 47 48 static struct { 49 unsigned int device_vendor; 50 unsigned char revision; 51 unsigned char content; 52 char fab_revision[8]; 53 char env_var[16]; 54 char env_setting[64]; 55 } expansion_config; 56 57 #if defined(CONFIG_CMD_NET) 58 static void setup_net_chip(void); 59 #endif 60 61 /* GPMC definitions for LAN9221 chips on Tobi expansion boards */ 62 static const u32 gpmc_lan_config[] = { 63 NET_LAN9221_GPMC_CONFIG1, 64 NET_LAN9221_GPMC_CONFIG2, 65 NET_LAN9221_GPMC_CONFIG3, 66 NET_LAN9221_GPMC_CONFIG4, 67 NET_LAN9221_GPMC_CONFIG5, 68 NET_LAN9221_GPMC_CONFIG6, 69 /*CONFIG7- computed as params */ 70 }; 71 72 /* 73 * Routine: board_init 74 * Description: Early hardware init. 75 */ 76 int board_init(void) 77 { 78 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 79 /* board id for Linux */ 80 gd->bd->bi_arch_number = MACH_TYPE_OVERO; 81 /* boot param addr */ 82 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 83 84 return 0; 85 } 86 87 /* 88 * Routine: get_board_revision 89 * Description: Returns the board revision 90 */ 91 int get_board_revision(void) 92 { 93 int revision; 94 95 #ifdef CONFIG_DRIVER_OMAP34XX_I2C 96 unsigned char data; 97 98 /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ 99 /* these boards should return a revision number of 0 */ 100 /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */ 101 i2c_set_bus_num(TWL4030_I2C_BUS); 102 data = 0x01; 103 i2c_write(0x4B, 0x29, 1, &data, 1); 104 data = 0x0c; 105 i2c_write(0x4B, 0x2b, 1, &data, 1); 106 i2c_read(0x4B, 0x2a, 1, &data, 1); 107 #endif 108 109 if (!gpio_request(112, "") && 110 !gpio_request(113, "") && 111 !gpio_request(115, "")) { 112 113 gpio_direction_input(112); 114 gpio_direction_input(113); 115 gpio_direction_input(115); 116 117 revision = gpio_get_value(115) << 2 | 118 gpio_get_value(113) << 1 | 119 gpio_get_value(112); 120 } else { 121 puts("Error: unable to acquire board revision GPIOs\n"); 122 revision = -1; 123 } 124 125 return revision; 126 } 127 128 #ifdef CONFIG_SPL_BUILD 129 /* 130 * Routine: get_board_mem_timings 131 * Description: If we use SPL then there is no x-loader nor config header 132 * so we have to setup the DDR timings ourself on both banks. 133 */ 134 void get_board_mem_timings(struct board_sdrc_timings *timings) 135 { 136 timings->mr = MICRON_V_MR_165; 137 switch (get_board_revision()) { 138 case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ 139 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 140 timings->ctrla = MICRON_V_ACTIMA_165; 141 timings->ctrlb = MICRON_V_ACTIMB_165; 142 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 143 break; 144 case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ 145 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 146 timings->ctrla = MICRON_V_ACTIMA_200; 147 timings->ctrlb = MICRON_V_ACTIMB_200; 148 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 149 break; 150 case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ 151 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 152 timings->ctrla = HYNIX_V_ACTIMA_200; 153 timings->ctrlb = HYNIX_V_ACTIMB_200; 154 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 155 break; 156 case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ 157 timings->mcfg = MCFG(512 << 20, 15); 158 timings->ctrla = MICRON_V_ACTIMA_200; 159 timings->ctrlb = MICRON_V_ACTIMB_200; 160 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 161 break; 162 default: 163 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 164 timings->ctrla = MICRON_V_ACTIMA_165; 165 timings->ctrlb = MICRON_V_ACTIMB_165; 166 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 167 } 168 } 169 #endif 170 171 /* 172 * Routine: get_sdio2_config 173 * Description: Return information about the wifi module connection 174 * Returns 0 if the module connects though a level translator 175 * Returns 1 if the module connects directly 176 */ 177 int get_sdio2_config(void) 178 { 179 int sdio_direct; 180 181 if (!gpio_request(130, "") && !gpio_request(139, "")) { 182 183 gpio_direction_output(130, 0); 184 gpio_direction_input(139); 185 186 sdio_direct = 1; 187 gpio_set_value(130, 0); 188 if (gpio_get_value(139) == 0) { 189 gpio_set_value(130, 1); 190 if (gpio_get_value(139) == 1) 191 sdio_direct = 0; 192 } 193 194 gpio_direction_input(130); 195 } else { 196 puts("Error: unable to acquire sdio2 clk GPIOs\n"); 197 sdio_direct = -1; 198 } 199 200 return sdio_direct; 201 } 202 203 /* 204 * Routine: get_expansion_id 205 * Description: This function checks for expansion board by checking I2C 206 * bus 2 for the availability of an AT24C01B serial EEPROM. 207 * returns the device_vendor field from the EEPROM 208 */ 209 unsigned int get_expansion_id(void) 210 { 211 i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); 212 213 /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */ 214 if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) { 215 i2c_set_bus_num(TWL4030_I2C_BUS); 216 return GUMSTIX_NO_EEPROM; 217 } 218 219 /* read configuration data */ 220 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, 221 sizeof(expansion_config)); 222 223 i2c_set_bus_num(TWL4030_I2C_BUS); 224 225 return expansion_config.device_vendor; 226 } 227 228 /* 229 * Routine: misc_init_r 230 * Description: Configure board specific parts 231 */ 232 int misc_init_r(void) 233 { 234 twl4030_power_init(); 235 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 236 237 #if defined(CONFIG_CMD_NET) 238 setup_net_chip(); 239 #endif 240 241 printf("Board revision: %d\n", get_board_revision()); 242 243 switch (get_sdio2_config()) { 244 case 0: 245 puts("Tranceiver detected on mmc2\n"); 246 MUX_OVERO_SDIO2_TRANSCEIVER(); 247 break; 248 case 1: 249 puts("Direct connection on mmc2\n"); 250 MUX_OVERO_SDIO2_DIRECT(); 251 break; 252 default: 253 puts("Unable to detect mmc2 connection type\n"); 254 } 255 256 switch (get_expansion_id()) { 257 case GUMSTIX_SUMMIT: 258 printf("Recognized Summit expansion board (rev %d %s)\n", 259 expansion_config.revision, 260 expansion_config.fab_revision); 261 setenv("defaultdisplay", "dvi"); 262 break; 263 case GUMSTIX_TOBI: 264 printf("Recognized Tobi expansion board (rev %d %s)\n", 265 expansion_config.revision, 266 expansion_config.fab_revision); 267 setenv("defaultdisplay", "dvi"); 268 break; 269 case GUMSTIX_TOBI_DUO: 270 printf("Recognized Tobi Duo expansion board (rev %d %s)\n", 271 expansion_config.revision, 272 expansion_config.fab_revision); 273 /* second lan chip */ 274 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 275 0x2B000000, GPMC_SIZE_16M); 276 break; 277 case GUMSTIX_PALO35: 278 printf("Recognized Palo35 expansion board (rev %d %s)\n", 279 expansion_config.revision, 280 expansion_config.fab_revision); 281 setenv("defaultdisplay", "lcd35"); 282 break; 283 case GUMSTIX_PALO43: 284 printf("Recognized Palo43 expansion board (rev %d %s)\n", 285 expansion_config.revision, 286 expansion_config.fab_revision); 287 setenv("defaultdisplay", "lcd43"); 288 break; 289 case GUMSTIX_CHESTNUT43: 290 printf("Recognized Chestnut43 expansion board (rev %d %s)\n", 291 expansion_config.revision, 292 expansion_config.fab_revision); 293 setenv("defaultdisplay", "lcd43"); 294 break; 295 case GUMSTIX_PINTO: 296 printf("Recognized Pinto expansion board (rev %d %s)\n", 297 expansion_config.revision, 298 expansion_config.fab_revision); 299 break; 300 case GUMSTIX_GALLOP43: 301 printf("Recognized Gallop43 expansion board (rev %d %s)\n", 302 expansion_config.revision, 303 expansion_config.fab_revision); 304 setenv("defaultdisplay", "lcd43"); 305 break; 306 case ETTUS_USRP_E: 307 printf("Recognized Ettus Research USRP-E (rev %d %s)\n", 308 expansion_config.revision, 309 expansion_config.fab_revision); 310 MUX_USRP_E(); 311 setenv("defaultdisplay", "dvi"); 312 break; 313 case GUMSTIX_NO_EEPROM: 314 puts("No EEPROM on expansion board\n"); 315 break; 316 default: 317 puts("Unrecognized expansion board\n"); 318 } 319 320 if (expansion_config.content == 1) 321 setenv(expansion_config.env_var, expansion_config.env_setting); 322 323 dieid_num_r(); 324 325 return 0; 326 } 327 328 /* 329 * Routine: set_muxconf_regs 330 * Description: Setting up the configuration Mux registers specific to the 331 * hardware. Many pins need to be moved from protect to primary 332 * mode. 333 */ 334 void set_muxconf_regs(void) 335 { 336 MUX_OVERO(); 337 } 338 339 #if defined(CONFIG_CMD_NET) 340 /* 341 * Routine: setup_net_chip 342 * Description: Setting up the configuration GPMC registers specific to the 343 * Ethernet hardware. 344 */ 345 static void setup_net_chip(void) 346 { 347 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 348 349 /* first lan chip */ 350 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 351 GPMC_SIZE_16M); 352 353 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 354 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 355 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 356 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 357 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 358 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 359 &ctrl_base->gpmc_nadv_ale); 360 361 /* Make GPIO 64 as output pin and send a magic pulse through it */ 362 if (!gpio_request(64, "")) { 363 gpio_direction_output(64, 0); 364 gpio_set_value(64, 1); 365 udelay(1); 366 gpio_set_value(64, 0); 367 udelay(1); 368 gpio_set_value(64, 1); 369 } 370 } 371 #endif 372 373 int board_eth_init(bd_t *bis) 374 { 375 int rc = 0; 376 #ifdef CONFIG_SMC911X 377 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 378 #endif 379 return rc; 380 } 381 382 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 383 int board_mmc_init(bd_t *bis) 384 { 385 return omap_mmc_init(0, 0, 0, -1, -1); 386 } 387 #endif 388