1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
264a93860SMarek Vasut /*
364a93860SMarek Vasut  * Olimex MX23 Olinuxino Boot setup
464a93860SMarek Vasut  *
564a93860SMarek Vasut  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
664a93860SMarek Vasut  */
764a93860SMarek Vasut 
864a93860SMarek Vasut #include <common.h>
964a93860SMarek Vasut #include <config.h>
1064a93860SMarek Vasut #include <asm/io.h>
1164a93860SMarek Vasut #include <asm/arch/iomux-mx23.h>
1264a93860SMarek Vasut #include <asm/arch/imx-regs.h>
1364a93860SMarek Vasut #include <asm/arch/sys_proto.h>
1464a93860SMarek Vasut 
1583284a1aSFabio Estevam #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
160b323439SFabio Estevam #define	MUX_CONFIG_SSP	(MXS_PAD_8MA | MXS_PAD_PULLUP)
1764a93860SMarek Vasut 
1864a93860SMarek Vasut const iomux_cfg_t iomux_setup[] = {
1964a93860SMarek Vasut 	/* DUART */
2064a93860SMarek Vasut 	MX23_PAD_PWM0__DUART_RX,
2164a93860SMarek Vasut 	MX23_PAD_PWM1__DUART_TX,
2264a93860SMarek Vasut 
2364a93860SMarek Vasut 	/* EMI */
2464a93860SMarek Vasut 	MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
2564a93860SMarek Vasut 	MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
2664a93860SMarek Vasut 	MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
2764a93860SMarek Vasut 	MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
2864a93860SMarek Vasut 	MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
2964a93860SMarek Vasut 	MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
3064a93860SMarek Vasut 	MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
3164a93860SMarek Vasut 	MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
3264a93860SMarek Vasut 	MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
3364a93860SMarek Vasut 	MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
3464a93860SMarek Vasut 	MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
3564a93860SMarek Vasut 	MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
3664a93860SMarek Vasut 	MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
3764a93860SMarek Vasut 	MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
3864a93860SMarek Vasut 	MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
3964a93860SMarek Vasut 	MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
4064a93860SMarek Vasut 	MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
4164a93860SMarek Vasut 	MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
4264a93860SMarek Vasut 	MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
4364a93860SMarek Vasut 	MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
4464a93860SMarek Vasut 	MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
4564a93860SMarek Vasut 	MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
4664a93860SMarek Vasut 
4764a93860SMarek Vasut 	MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
4864a93860SMarek Vasut 	MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
4964a93860SMarek Vasut 	MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
5064a93860SMarek Vasut 	MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
5164a93860SMarek Vasut 	MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
5264a93860SMarek Vasut 	MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
5364a93860SMarek Vasut 	MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
5464a93860SMarek Vasut 	MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
5564a93860SMarek Vasut 	MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
5664a93860SMarek Vasut 	MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
5764a93860SMarek Vasut 	MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
5864a93860SMarek Vasut 	MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
5964a93860SMarek Vasut 	MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
6064a93860SMarek Vasut 	MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
6164a93860SMarek Vasut 	MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
6264a93860SMarek Vasut 
6364a93860SMarek Vasut 	MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
6464a93860SMarek Vasut 	MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
6564a93860SMarek Vasut 	MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
6664a93860SMarek Vasut 	MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
6764a93860SMarek Vasut 	MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
6864a93860SMarek Vasut 	MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
6913b1ebdeSMarek Vasut 
7036c7c925SOtavio Salvador 	/* Green LED */
7136c7c925SOtavio Salvador 	MX23_PAD_SSP1_DETECT__GPIO_2_1 |
7236c7c925SOtavio Salvador 		(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
7336c7c925SOtavio Salvador 
7413b1ebdeSMarek Vasut 	/* MMC 0 */
7513b1ebdeSMarek Vasut 	MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
7613b1ebdeSMarek Vasut 	MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
7713b1ebdeSMarek Vasut 	MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
7813b1ebdeSMarek Vasut 	MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
7913b1ebdeSMarek Vasut 	MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
8013b1ebdeSMarek Vasut 	MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
81ebe1d170SOtavio Salvador 
82ebe1d170SOtavio Salvador 	/* Ethernet */
83ebe1d170SOtavio Salvador 	MX23_PAD_GPMI_ALE__GPIO_0_17 |
84ebe1d170SOtavio Salvador 		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
8564a93860SMarek Vasut };
8664a93860SMarek Vasut 
board_init_ll(const uint32_t arg,const uint32_t * resptr)877b8657e2SMarek Vasut void board_init_ll(const uint32_t arg, const uint32_t *resptr)
8864a93860SMarek Vasut {
897b8657e2SMarek Vasut 	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
9064a93860SMarek Vasut }
917ae350a0SJan Luebbe 
927ae350a0SJan Luebbe /* Fine-tune the DRAM configuration. */
mxs_adjust_memory_params(uint32_t * dram_vals)937ae350a0SJan Luebbe void mxs_adjust_memory_params(uint32_t *dram_vals)
947ae350a0SJan Luebbe {
957ae350a0SJan Luebbe 	/* Enable Auto Precharge. */
967ae350a0SJan Luebbe 	dram_vals[3] |= 1 << 8;
977ae350a0SJan Luebbe 	/* Enable Fast Writes. */
987ae350a0SJan Luebbe 	dram_vals[5] |= 1 << 8;
997ae350a0SJan Luebbe 	/* tEMRS = 3*tCK */
1007ae350a0SJan Luebbe 	dram_vals[10] &= ~(0x3 << 8);
1017ae350a0SJan Luebbe 	dram_vals[10] |= (0x3 << 8);
1027ae350a0SJan Luebbe 	/* CASLAT = 3*tCK */
1037ae350a0SJan Luebbe 	dram_vals[11] &= ~(0x3 << 0);
1047ae350a0SJan Luebbe 	dram_vals[11] |= (0x3 << 0);
1057ae350a0SJan Luebbe 	/* tCKE = 1*tCK */
1067ae350a0SJan Luebbe 	dram_vals[12] &= ~(0x7 << 0);
1077ae350a0SJan Luebbe 	dram_vals[12] |= (0x1 << 0);
1087ae350a0SJan Luebbe 	/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
1097ae350a0SJan Luebbe 	dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
1107ae350a0SJan Luebbe 	dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
1117ae350a0SJan Luebbe 	/* tDAL = 6*tCK */
1127ae350a0SJan Luebbe 	dram_vals[15] &= ~(0xf << 16);
1137ae350a0SJan Luebbe 	dram_vals[15] |= (0x6 << 16);
1147ae350a0SJan Luebbe 	/* tREF = 1040*tCK */
1157ae350a0SJan Luebbe 	dram_vals[26] &= ~0xffff;
1167ae350a0SJan Luebbe 	dram_vals[26] |= 0x0410;
1177ae350a0SJan Luebbe 	/* tRAS_MAX = 9334*tCK */
1187ae350a0SJan Luebbe 	dram_vals[32] &= ~0xffff;
1197ae350a0SJan Luebbe 	dram_vals[32] |= 0x2475;
1207ae350a0SJan Luebbe }
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