1 /*
2  * Olimex MX23 Olinuxino board
3  *
4  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <asm/gpio.h>
11 #include <asm/io.h>
12 #include <asm/arch/iomux-mx23.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #ifdef CONFIG_STATUS_LED
17 #include <status_led.h>
18 #endif
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 /*
23  * Functions
24  */
25 int board_early_init_f(void)
26 {
27 	/* IO0 clock at 480MHz */
28 	mxs_set_ioclk(MXC_IOCLK0, 480000);
29 
30 	/* SSP0 clock at 96MHz */
31 	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
32 
33 	return 0;
34 }
35 
36 #ifdef CONFIG_CMD_USB
37 int board_ehci_hcd_init(int port)
38 {
39 	/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
40 	gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
41 	udelay(100);
42 	return 0;
43 }
44 
45 int board_ehci_hcd_exit(int port)
46 {
47 	/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
48 	gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0);
49 	return 0;
50 }
51 #endif
52 
53 int dram_init(void)
54 {
55 	return mxs_dram_init();
56 }
57 
58 #ifdef	CONFIG_CMD_MMC
59 static int mx23_olx_mmc_cd(int id)
60 {
61 	return 1;	/* Card always present */
62 }
63 
64 int board_mmc_init(bd_t *bis)
65 {
66 	return mxsmmc_initialize(bis, 0, NULL, mx23_olx_mmc_cd);
67 }
68 #endif
69 
70 int board_init(void)
71 {
72 	/* Adress of boot parameters */
73 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
74 
75 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
76 	status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE);
77 #endif
78 
79 	return 0;
80 }
81 
82 /* Fine-tune the DRAM configuration. */
83 void mxs_adjust_memory_params(uint32_t *dram_vals)
84 {
85 	/* Enable Auto Precharge. */
86 	dram_vals[3] |= 1 << 8;
87 	/* Enable Fast Writes. */
88 	dram_vals[5] |= 1 << 8;
89 	/* tEMRS = 3*tCK */
90 	dram_vals[10] &= ~(0x3 << 8);
91 	dram_vals[10] |= (0x3 << 8);
92 	/* CASLAT = 3*tCK */
93 	dram_vals[11] &= ~(0x3 << 0);
94 	dram_vals[11] |= (0x3 << 0);
95 	/* tCKE = 1*tCK */
96 	dram_vals[12] &= ~(0x7 << 0);
97 	dram_vals[12] |= (0x1 << 0);
98 	/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
99 	dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
100 	dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
101 	/* tDAL = 6*tCK */
102 	dram_vals[15] &= ~(0xf << 16);
103 	dram_vals[15] |= (0x6 << 16);
104 	/* tREF = 1040*tCK */
105 	dram_vals[26] &= ~0xffff;
106 	dram_vals[26] |= 0x0410;
107 	/* tRAS_MAX = 9334*tCK */
108 	dram_vals[32] &= ~0xffff;
109 	dram_vals[32] |= 0x2475;
110 }
111