1 /* 2 * (C) Copyright 2013 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _PINMUX_CONFIG_VENICE2_H_ 9 #define _PINMUX_CONFIG_VENICE2_H_ 10 11 #define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ 12 { \ 13 .pingrp = PMUX_PINGRP_##_pingrp, \ 14 .func = PMUX_FUNC_##_mux, \ 15 .pull = PMUX_PULL_##_pull, \ 16 .tristate = PMUX_TRI_##_tri, \ 17 .io = PMUX_PIN_##_io, \ 18 .lock = PMUX_PIN_LOCK_DEFAULT, \ 19 .od = PMUX_PIN_OD_DEFAULT, \ 20 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 21 } 22 23 #define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ 24 { \ 25 .pingrp = PMUX_PINGRP_##_pingrp, \ 26 .func = PMUX_FUNC_##_mux, \ 27 .pull = PMUX_PULL_##_pull, \ 28 .tristate = PMUX_TRI_##_tri, \ 29 .io = PMUX_PIN_##_io, \ 30 .lock = PMUX_PIN_LOCK_##_lock, \ 31 .od = PMUX_PIN_OD_##_od, \ 32 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 33 } 34 35 #define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ 36 { \ 37 .pingrp = PMUX_PINGRP_##_pingrp, \ 38 .func = PMUX_FUNC_##_mux, \ 39 .pull = PMUX_PULL_##_pull, \ 40 .tristate = PMUX_TRI_##_tri, \ 41 .io = PMUX_PIN_##_io, \ 42 .lock = PMUX_PIN_LOCK_##_lock, \ 43 .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ 44 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 45 } 46 47 #define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ 48 { \ 49 .pingrp = PMUX_PINGRP_##_pingrp, \ 50 .func = PMUX_FUNC_##_mux, \ 51 .pull = PMUX_PULL_##_pull, \ 52 .tristate = PMUX_TRI_##_tri, \ 53 .io = PMUX_PIN_##_io, \ 54 .lock = PMUX_PIN_LOCK_##_lock, \ 55 .od = PMUX_PIN_OD_DEFAULT, \ 56 .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ 57 } 58 59 #define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ 60 { \ 61 .pingrp = PMUX_PINGRP_##_pingrp, \ 62 .func = PMUX_FUNC_##_mux, \ 63 .pull = PMUX_PULL_##_pull, \ 64 .tristate = PMUX_TRI_##_tri, \ 65 .io = PMUX_PIN_##_io, \ 66 .lock = PMUX_PIN_LOCK_##_lock, \ 67 .od = PMUX_PIN_OD_##_od, \ 68 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 69 } 70 71 #define USB_PINMUX CEC_PINMUX 72 73 #define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ 74 { \ 75 .drvgrp = PMUX_DRVGRP_##_drvgrp, \ 76 .slwf = _slwf, \ 77 .slwr = _slwr, \ 78 .drvup = _drvup, \ 79 .drvdn = _drvdn, \ 80 .lpmd = PMUX_LPMD_##_lpmd, \ 81 .schmt = PMUX_SCHMT_##_schmt, \ 82 .hsm = PMUX_HSM_##_hsm, \ 83 } 84 85 static struct pmux_pingrp_config tegra124_pinmux_common[] = { 86 /* EXTPERIPH1 pinmux */ 87 DEFAULT_PINMUX(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), 88 89 /* I2S0 pinmux */ 90 DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT), 91 DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), 92 DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), 93 DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), 94 95 /* I2S1 pinmux */ 96 DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT), 97 DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), 98 DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), 99 DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), 100 101 /* I2S3 pinmux */ 102 DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), 103 DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), 104 DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), 105 DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), 106 107 /* CLDVFS pinmux */ 108 DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT), 109 DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT), 110 111 /* ULPI pinmux */ 112 DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT), 113 DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT), 114 DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT), 115 DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT), 116 DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT), 117 DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, UP, NORMAL, INPUT), 118 DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT), 119 120 /* EC KBC/SPI */ 121 DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, UP, NORMAL, INPUT), 122 DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, UP, NORMAL, INPUT), 123 DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT), 124 DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT), 125 126 /* I2C3 (TPM) pinmux */ 127 I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 128 I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 129 130 /* I2C2 pinmux */ 131 I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 132 I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 133 134 /* UARTD pinmux (UART4 on Servo board, unused) */ 135 DEFAULT_PINMUX(PJ7, UARTD, NORMAL, NORMAL, OUTPUT), 136 DEFAULT_PINMUX(PB0, UARTD, NORMAL, TRISTATE, INPUT), 137 DEFAULT_PINMUX(PB1, UARTD, NORMAL, TRISTATE, INPUT), 138 DEFAULT_PINMUX(PK7, UARTD, NORMAL, NORMAL, OUTPUT), 139 140 /* SPI4 (Winbond 'boot ROM') */ 141 DEFAULT_PINMUX(PG5, SPI4, NORMAL, NORMAL, INPUT), 142 DEFAULT_PINMUX(PG6, SPI4, UP, NORMAL, INPUT), 143 DEFAULT_PINMUX(PG7, SPI4, UP, NORMAL, INPUT), 144 DEFAULT_PINMUX(PI3, SPI4, NORMAL, NORMAL, INPUT), 145 146 /* Touch IRQ */ 147 DEFAULT_PINMUX(GPIO_W3_AUD_PW3, RSVD1, NORMAL, NORMAL, INPUT), 148 149 /* PWM1 pinmux */ 150 DEFAULT_PINMUX(PH1, PWM1, NORMAL, NORMAL, OUTPUT), 151 152 /* SDMMC1 pinmux */ 153 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), 154 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), 155 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), 156 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), 157 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), 158 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), 159 160 /* SDMMC3 pinmux */ 161 DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), 162 DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), 163 DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), 164 DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), 165 DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), 166 DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), 167 DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT), 168 DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT), 169 170 /* SDMMC4 pinmux */ 171 DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT), 172 DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT), 173 DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT), 174 DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT), 175 DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT), 176 DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT), 177 DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT), 178 DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT), 179 DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT), 180 DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT), 181 182 /* BLINK pinmux */ 183 DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), 184 185 /* KBC pinmux */ 186 DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), 187 DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), 188 DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), 189 DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), 190 DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), 191 192 /* Misc */ 193 DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), 194 DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT), 195 196 /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */ 197 DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, UP, NORMAL, OUTPUT), 198 DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT), 199 200 /* I2CPWR pinmux (I2C5) */ 201 I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 202 I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 203 204 /* RTCK pinmux */ 205 DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), 206 207 /* CLK pinmux */ 208 DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), 209 210 /* PWRON pinmux */ 211 DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), 212 213 /* CPU pinmux */ 214 DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), 215 216 /* PMI pinmux */ 217 DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), 218 219 /* RESET_OUT_N pinmux */ 220 DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), 221 222 /* EXTPERIPH3 pinmux */ 223 DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), 224 225 /* I2C1 pinmux */ 226 I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 227 I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 228 229 /* UARTB, GPS */ 230 DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT), 231 DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), 232 DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT), 233 DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT), 234 235 /* UARTC (WIFI/BT) */ 236 DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT), 237 DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), 238 DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT), 239 DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), 240 241 /* CEC pinmux */ 242 CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), 243 244 /* I2C4 (HDMI_DDC) pinmux */ 245 DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), 246 DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), 247 248 /* USB pinmux */ 249 USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 250 USB_PINMUX(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 251 252 /* Unused, marked SNN_ on schematic, TRISTATE 'em */ 253 DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, TRISTATE, INPUT), 254 DEFAULT_PINMUX(PBB3, RSVD3, NORMAL, TRISTATE, INPUT), 255 DEFAULT_PINMUX(PBB4, RSVD3, NORMAL, TRISTATE, INPUT), 256 DEFAULT_PINMUX(PBB5, RSVD2, NORMAL, TRISTATE, INPUT), 257 DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, TRISTATE, INPUT), 258 DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, TRISTATE, INPUT), 259 DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), 260 DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, TRISTATE, INPUT), 261 DEFAULT_PINMUX(PH3, GMI, NORMAL, TRISTATE, INPUT), 262 DEFAULT_PINMUX(PI7, GMI, NORMAL, TRISTATE, INPUT), 263 DEFAULT_PINMUX(PJ2, RSVD1, NORMAL, TRISTATE, INPUT), 264 DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD3, NORMAL, TRISTATE, INPUT), 265 DEFAULT_PINMUX(GPIO_X6_AUD_PX6, GMI, NORMAL, TRISTATE, INPUT), 266 DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, NORMAL, TRISTATE, INPUT), 267 DEFAULT_PINMUX(PFF2, RSVD1, NORMAL, TRISTATE, INPUT), 268 DEFAULT_PINMUX(USB_VBUS_EN2_PFF1, RSVD1, NORMAL, TRISTATE, INPUT), 269 DEFAULT_PINMUX(KB_COL5_PQ5, RSVD1, NORMAL, TRISTATE, INPUT), 270 DEFAULT_PINMUX(KB_ROW2_PR2, RSVD1, NORMAL, TRISTATE, INPUT), 271 DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, TRISTATE, INPUT), 272 DEFAULT_PINMUX(KB_ROW5_PR5, RSVD2, NORMAL, TRISTATE, INPUT), 273 DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), 274 DEFAULT_PINMUX(KB_ROW13_PS5, RSVD1, NORMAL, TRISTATE, INPUT), 275 DEFAULT_PINMUX(KB_ROW14_PS6, RSVD1, NORMAL, TRISTATE, INPUT), 276 DEFAULT_PINMUX(KB_ROW16_PT0, RSVD1, NORMAL, TRISTATE, INPUT), 277 DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT), 278 DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, TRISTATE, INPUT), 279 DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, INPUT), 280 DEFAULT_PINMUX(DAP3_FS_PP0, RSVD1, NORMAL, TRISTATE, INPUT), 281 DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD2, NORMAL, TRISTATE, INPUT), 282 DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD1, NORMAL, TRISTATE, INPUT), 283 DEFAULT_PINMUX(SDMMC1_WP_N_PV3, RSVD1, NORMAL, TRISTATE, INPUT), 284 DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, TRISTATE, INPUT), 285 DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, TRISTATE, INPUT), 286 DEFAULT_PINMUX(SPDIF_OUT_PK5, RSVD1, NORMAL, TRISTATE, INPUT), 287 }; 288 289 static struct pmux_pingrp_config unused_pins_lowpower[] = { 290 DEFAULT_PINMUX(DAP_MCLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT), 291 }; 292 293 /* Initially setting all used GPIO's to non-TRISTATE */ 294 static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = { 295 DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT), 296 DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT), 297 DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT), 298 DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT), 299 300 /* EN_VDD_BL */ 301 DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT), 302 303 /* MODEM */ 304 DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT), 305 DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), 306 307 /* BOOT_SEL0-3 */ 308 DEFAULT_PINMUX(PG0, GMI, NORMAL, NORMAL, INPUT), 309 DEFAULT_PINMUX(PG1, GMI, NORMAL, NORMAL, INPUT), 310 DEFAULT_PINMUX(PG2, GMI, NORMAL, NORMAL, INPUT), 311 DEFAULT_PINMUX(PG3, GMI, NORMAL, NORMAL, INPUT), 312 313 DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT), 314 315 DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT), 316 DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT), 317 DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT), 318 DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT), 319 DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT), 320 DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), 321 322 DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, INPUT), 323 DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, OUTPUT), 324 DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT), 325 326 DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT), 327 DEFAULT_PINMUX(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, INPUT), 328 DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT), 329 330 /* TS_SHDN_L */ 331 DEFAULT_PINMUX(PK1, GMI, NORMAL, NORMAL, OUTPUT), 332 }; 333 334 static struct pmux_drvgrp_config venice2_padctrl[] = { 335 /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ 336 DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, 337 SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), 338 }; 339 #endif /* PINMUX_CONFIG_VENICE2_H */ 340