1 /*
2  * (C) Copyright 2013
3  * NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7 
8 /* AS3722-PMIC-specific early init regs */
9 
10 #define AS3722_I2C_ADDR		0x80
11 
12 #define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
13 #define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
14 #define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
15 #define AS3722_SDCONTROL_REG	0x4D
16 
17 #define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
18 #define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC */
19 #define AS3722_LDCONTROL_REG	0x4E
20 
21 #if defined(CONFIG_TARGET_VENICE2)
22 #define AS3722_SD0VOLTAGE_DATA	(0x2800 | AS3722_SD0VOLTAGE_REG)
23 #else /* TK1 or Nyan-Big */
24 #define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
25 #endif
26 #define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
27 
28 #if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
29 #define AS3722_SD1VOLTAGE_DATA	(0x2800 | AS3722_SD1VOLTAGE_REG)
30 #define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
31 #endif
32 
33 #define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
34 #define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
35 
36 #define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
37 #define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
38 
39 #define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
40 #define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
41 
42 #define I2C_SEND_2_BYTES	0x0A02
43 
44 void pmic_enable_cpu_vdd(void);
45