1 /* 2 * (C) Copyright 2013 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch-tegra/tegra_i2c.h> 11 #include "as3722_init.h" 12 13 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */ 14 15 void tegra_i2c_ll_write_addr(uint addr, uint config) 16 { 17 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; 18 19 writel(addr, ®->cmd_addr0); 20 writel(config, ®->cnfg); 21 } 22 23 void tegra_i2c_ll_write_data(uint data, uint config) 24 { 25 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; 26 27 writel(data, ®->cmd_data1); 28 writel(config, ®->cnfg); 29 } 30 31 void pmic_enable_cpu_vdd(void) 32 { 33 debug("%s entry\n", __func__); 34 35 #ifdef AS3722_SD1VOLTAGE_DATA 36 /* Set up VDD_CORE, for boards where OTP is incorrect*/ 37 debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__); 38 /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */ 39 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 40 tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES); 41 /* 42 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 43 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES); 44 */ 45 udelay(10 * 1000); 46 #endif 47 48 debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); 49 /* 50 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. 51 * First set VDD to 1.0V, then enable the VDD regulator. 52 */ 53 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 54 tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES); 55 /* 56 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 57 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES); 58 */ 59 udelay(10 * 1000); 60 61 debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__); 62 /* 63 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus. 64 * First set VDD to 1.0V, then enable the VDD regulator. 65 */ 66 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 67 tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES); 68 /* 69 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 70 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES); 71 */ 72 udelay(10 * 1000); 73 74 debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__); 75 /* 76 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus. 77 * First set VDD to 1.2V, then enable the VDD regulator. 78 */ 79 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 80 tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES); 81 /* 82 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. 83 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES); 84 */ 85 udelay(10 * 1000); 86 87 debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__); 88 /* 89 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. 90 * First set it to bypass 3.3V straight thru, then enable the regulator 91 * 92 * NOTE: We do this early because doing it later seems to hose the CPU 93 * power rail/partition startup. Need to debug. 94 */ 95 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 96 tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES); 97 /* 98 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. 99 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES); 100 */ 101 udelay(10 * 1000); 102 } 103