1f7dc4ac3STom Warren /* 2f7dc4ac3STom Warren * (C) Copyright 2013 3f7dc4ac3STom Warren * NVIDIA Corporation <www.nvidia.com> 4f7dc4ac3STom Warren * 5f7dc4ac3STom Warren * SPDX-License-Identifier: GPL-2.0+ 6f7dc4ac3STom Warren */ 7f7dc4ac3STom Warren 8f7dc4ac3STom Warren #include <common.h> 9f7dc4ac3STom Warren #include <asm/io.h> 10f7dc4ac3STom Warren #include <asm/arch-tegra/tegra_i2c.h> 11f7dc4ac3STom Warren #include "as3722_init.h" 12f7dc4ac3STom Warren 13f7dc4ac3STom Warren /* AS3722-PMIC-specific early init code - get CPU rails up, etc */ 14f7dc4ac3STom Warren 15f7dc4ac3STom Warren void tegra_i2c_ll_write_addr(uint addr, uint config) 16f7dc4ac3STom Warren { 17f7dc4ac3STom Warren struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; 18f7dc4ac3STom Warren 19f7dc4ac3STom Warren writel(addr, ®->cmd_addr0); 20f7dc4ac3STom Warren writel(config, ®->cnfg); 21f7dc4ac3STom Warren } 22f7dc4ac3STom Warren 23f7dc4ac3STom Warren void tegra_i2c_ll_write_data(uint data, uint config) 24f7dc4ac3STom Warren { 25f7dc4ac3STom Warren struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; 26f7dc4ac3STom Warren 27f7dc4ac3STom Warren writel(data, ®->cmd_data1); 28f7dc4ac3STom Warren writel(config, ®->cnfg); 29f7dc4ac3STom Warren } 30f7dc4ac3STom Warren 31f7dc4ac3STom Warren void pmic_enable_cpu_vdd(void) 32f7dc4ac3STom Warren { 33f7dc4ac3STom Warren debug("%s entry\n", __func__); 34f7dc4ac3STom Warren 35*b064c912SBibek Basu #ifdef AS3722_SD1VOLTAGE_DATA 36*b064c912SBibek Basu /* Set up VDD_CORE, for boards where OTP is incorrect*/ 37*b064c912SBibek Basu debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__); 38*b064c912SBibek Basu /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */ 39*b064c912SBibek Basu tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 40*b064c912SBibek Basu tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES); 41*b064c912SBibek Basu /* 42*b064c912SBibek Basu * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 43*b064c912SBibek Basu * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES); 44*b064c912SBibek Basu */ 45*b064c912SBibek Basu udelay(10 * 1000); 46*b064c912SBibek Basu #endif 47f7dc4ac3STom Warren 48f7dc4ac3STom Warren debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); 49f7dc4ac3STom Warren /* 50f7dc4ac3STom Warren * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. 51f7dc4ac3STom Warren * First set VDD to 1.0V, then enable the VDD regulator. 52f7dc4ac3STom Warren */ 53f7dc4ac3STom Warren tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 54f7dc4ac3STom Warren tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES); 55f7dc4ac3STom Warren /* 56f7dc4ac3STom Warren * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 57f7dc4ac3STom Warren * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES); 58f7dc4ac3STom Warren */ 59f7dc4ac3STom Warren udelay(10 * 1000); 60f7dc4ac3STom Warren 61f7dc4ac3STom Warren debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__); 62f7dc4ac3STom Warren /* 63f7dc4ac3STom Warren * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus. 64f7dc4ac3STom Warren * First set VDD to 1.0V, then enable the VDD regulator. 65f7dc4ac3STom Warren */ 66f7dc4ac3STom Warren tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 67f7dc4ac3STom Warren tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES); 68f7dc4ac3STom Warren /* 69f7dc4ac3STom Warren * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 70f7dc4ac3STom Warren * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES); 71f7dc4ac3STom Warren */ 72f7dc4ac3STom Warren udelay(10 * 1000); 73f7dc4ac3STom Warren 74f7dc4ac3STom Warren debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__); 75f7dc4ac3STom Warren /* 76f7dc4ac3STom Warren * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus. 77f7dc4ac3STom Warren * First set VDD to 1.2V, then enable the VDD regulator. 78f7dc4ac3STom Warren */ 79f7dc4ac3STom Warren tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 80f7dc4ac3STom Warren tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES); 81f7dc4ac3STom Warren /* 82f7dc4ac3STom Warren * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. 83f7dc4ac3STom Warren * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES); 84f7dc4ac3STom Warren */ 85f7dc4ac3STom Warren udelay(10 * 1000); 86f7dc4ac3STom Warren 87f7dc4ac3STom Warren debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__); 88f7dc4ac3STom Warren /* 89f7dc4ac3STom Warren * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. 90f7dc4ac3STom Warren * First set it to bypass 3.3V straight thru, then enable the regulator 91f7dc4ac3STom Warren * 92f7dc4ac3STom Warren * NOTE: We do this early because doing it later seems to hose the CPU 93f7dc4ac3STom Warren * power rail/partition startup. Need to debug. 94f7dc4ac3STom Warren */ 95f7dc4ac3STom Warren tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 96f7dc4ac3STom Warren tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES); 97f7dc4ac3STom Warren /* 98f7dc4ac3STom Warren * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. 99f7dc4ac3STom Warren * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES); 100f7dc4ac3STom Warren */ 101f7dc4ac3STom Warren udelay(10 * 1000); 102f7dc4ac3STom Warren } 103