1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2014
4  * NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <asm/gpio.h>
11 #include <asm/io.h>
12 #include <asm/arch/pinmux.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/mc.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <power/as3722.h>
18 #include <power/pmic.h>
19 #include "pinmux-config-nyan-big.h"
20 
21 /*
22  * Routine: pinmux_init
23  * Description: Do individual peripheral pinmux configs
24  */
25 void pinmux_init(void)
26 {
27 	gpio_config_table(nyan_big_gpio_inits,
28 			  ARRAY_SIZE(nyan_big_gpio_inits));
29 
30 	pinmux_config_pingrp_table(nyan_big_pingrps,
31 				   ARRAY_SIZE(nyan_big_pingrps));
32 
33 	pinmux_config_drvgrp_table(nyan_big_drvgrps,
34 				   ARRAY_SIZE(nyan_big_drvgrps));
35 }
36 
37 int tegra_board_id(void)
38 {
39 	static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
40 					TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
41 					-1};
42 
43 	gpio_claim_vector(vector, "board_id%d");
44 	return gpio_get_values_as_int(vector);
45 }
46 
47 int tegra_lcd_pmic_init(int board_id)
48 {
49 	struct udevice *dev;
50 	int ret;
51 
52 	ret = uclass_get_device_by_driver(UCLASS_PMIC,
53 					  DM_GET_DRIVER(pmic_as3722), &dev);
54 	if (ret) {
55 		debug("%s: Failed to find PMIC\n", __func__);
56 		return ret;
57 	}
58 
59 	if (board_id == 0)
60 		pmic_reg_write(dev, 0x00, 0x3c);
61 	else
62 		pmic_reg_write(dev, 0x00, 0x50);
63 	pmic_reg_write(dev, 0x12, 0x10);
64 	pmic_reg_write(dev, 0x0c, 0x07);
65 	pmic_reg_write(dev, 0x20, 0x10);
66 
67 	return 0;
68 }
69 
70 /* Setup required information for Linux kernel */
71 static void setup_kernel_info(void)
72 {
73 	struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
74 
75 	/* The kernel graphics driver needs this region locked down */
76 	writel(0, &mc->mc_video_protect_bom);
77 	writel(0, &mc->mc_video_protect_size_mb);
78 	writel(1, &mc->mc_video_protect_reg_ctrl);
79 }
80 
81 /*
82  * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
83  * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
84  * Otherwise reading AHUB devices will hang when the kernel boots.
85  */
86 static void enable_required_clocks(void)
87 {
88 	static enum periph_id ids[] = {
89 		PERIPH_ID_I2S0,
90 		PERIPH_ID_I2S1,
91 		PERIPH_ID_I2S2,
92 		PERIPH_ID_I2S3,
93 		PERIPH_ID_I2S4,
94 		PERIPH_ID_AUDIO,
95 		PERIPH_ID_APBIF,
96 		PERIPH_ID_DAM0,
97 		PERIPH_ID_DAM1,
98 		PERIPH_ID_DAM2,
99 		PERIPH_ID_AMX0,
100 		PERIPH_ID_AMX1,
101 		PERIPH_ID_ADX0,
102 		PERIPH_ID_ADX1,
103 		PERIPH_ID_SPDIF,
104 		PERIPH_ID_AFC0,
105 		PERIPH_ID_AFC1,
106 		PERIPH_ID_AFC2,
107 		PERIPH_ID_AFC3,
108 		PERIPH_ID_AFC4,
109 		PERIPH_ID_AFC5,
110 		PERIPH_ID_EXTPERIPH1
111 	};
112 	int i;
113 
114 	for (i = 0; i < ARRAY_SIZE(ids); i++)
115 		clock_enable(ids[i]);
116 	udelay(2);
117 	for (i = 0; i < ARRAY_SIZE(ids); i++)
118 		reset_set_enable(ids[i], 0);
119 }
120 
121 int nvidia_board_init(void)
122 {
123 	clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
124 	clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
125 
126 	/* For external MAX98090 audio codec */
127 	clock_external_output(1);
128 	setup_kernel_info();
129 	enable_required_clocks();
130 
131 	return 0;
132 }
133