1 /* 2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef _PINMUX_CONFIG_DALMORE_H_ 18 #define _PINMUX_CONFIG_DALMORE_H_ 19 20 #define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ 21 { \ 22 .pingrp = PMUX_PINGRP_##_pingrp, \ 23 .func = PMUX_FUNC_##_mux, \ 24 .pull = PMUX_PULL_##_pull, \ 25 .tristate = PMUX_TRI_##_tri, \ 26 .io = PMUX_PIN_##_io, \ 27 .lock = PMUX_PIN_LOCK_DEFAULT, \ 28 .od = PMUX_PIN_OD_DEFAULT, \ 29 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 30 } 31 32 #define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ 33 { \ 34 .pingrp = PMUX_PINGRP_##_pingrp, \ 35 .func = PMUX_FUNC_##_mux, \ 36 .pull = PMUX_PULL_##_pull, \ 37 .tristate = PMUX_TRI_##_tri, \ 38 .io = PMUX_PIN_##_io, \ 39 .lock = PMUX_PIN_LOCK_##_lock, \ 40 .od = PMUX_PIN_OD_##_od, \ 41 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 42 } 43 44 #define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ 45 { \ 46 .pingrp = PMUX_PINGRP_##_pingrp, \ 47 .func = PMUX_FUNC_##_mux, \ 48 .pull = PMUX_PULL_##_pull, \ 49 .tristate = PMUX_TRI_##_tri, \ 50 .io = PMUX_PIN_##_io, \ 51 .lock = PMUX_PIN_LOCK_##_lock, \ 52 .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ 53 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 54 } 55 56 #define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ 57 { \ 58 .pingrp = PMUX_PINGRP_##_pingrp, \ 59 .func = PMUX_FUNC_##_mux, \ 60 .pull = PMUX_PULL_##_pull, \ 61 .tristate = PMUX_TRI_##_tri, \ 62 .io = PMUX_PIN_##_io, \ 63 .lock = PMUX_PIN_LOCK_##_lock, \ 64 .od = PMUX_PIN_OD_DEFAULT, \ 65 .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ 66 } 67 68 #define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ 69 { \ 70 .pingrp = PMUX_PINGRP_##_pingrp, \ 71 .func = PMUX_FUNC_##_mux, \ 72 .pull = PMUX_PULL_##_pull, \ 73 .tristate = PMUX_TRI_##_tri, \ 74 .io = PMUX_PIN_##_io, \ 75 .lock = PMUX_PIN_LOCK_##_lock, \ 76 .od = PMUX_PIN_OD_##_od, \ 77 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 78 } 79 80 #define USB_PINMUX CEC_PINMUX 81 82 #define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ 83 { \ 84 .drvgrp = PMUX_DRVGRP_##_drvgrp, \ 85 .slwf = _slwf, \ 86 .slwr = _slwr, \ 87 .drvup = _drvup, \ 88 .drvdn = _drvdn, \ 89 .lpmd = PMUX_LPMD_##_lpmd, \ 90 .schmt = PMUX_SCHMT_##_schmt, \ 91 .hsm = PMUX_HSM_##_hsm, \ 92 } 93 94 static struct pmux_pingrp_config tegra114_pinmux_common[] = { 95 /* EXTPERIPH1 pinmux */ 96 DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), 97 98 /* I2S0 pinmux */ 99 DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT), 100 DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), 101 DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), 102 DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), 103 104 /* I2S1 pinmux */ 105 DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT), 106 DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), 107 DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), 108 DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), 109 110 /* I2S3 pinmux */ 111 DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), 112 DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), 113 DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), 114 DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), 115 116 /* CLDVFS pinmux */ 117 DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT), 118 DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT), 119 120 /* ULPI pinmux */ 121 DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, NORMAL, INPUT), 122 DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT), 123 DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT), 124 DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT), 125 DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT), 126 DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, NORMAL, NORMAL, INPUT), 127 DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT), 128 DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT), 129 DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, NORMAL, INPUT), 130 DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, INPUT), 131 DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, TRISTATE, INPUT), 132 DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, OUTPUT), 133 134 /* I2C3 pinmux */ 135 I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 136 I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 137 138 /* VI pinmux */ 139 VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), 140 141 /* VI_ALT1 pinmux */ 142 VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), 143 144 /* VGP4 pinmux */ 145 VI_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), 146 147 /* I2C2 pinmux */ 148 I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 149 I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 150 151 /* UARTD pinmux */ 152 DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), 153 DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, TRISTATE, INPUT), 154 DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, TRISTATE, INPUT), 155 DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), 156 157 /* SPI4 pinmux */ 158 DEFAULT_PINMUX(GMI_AD5_PG5, SPI4, NORMAL, NORMAL, INPUT), 159 DEFAULT_PINMUX(GMI_AD6_PG6, SPI4, UP, NORMAL, INPUT), 160 DEFAULT_PINMUX(GMI_AD7_PG7, SPI4, UP, NORMAL, INPUT), 161 DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, OUTPUT), 162 DEFAULT_PINMUX(GMI_CS6_N_PI3, SPI4, NORMAL, NORMAL, INPUT), 163 DEFAULT_PINMUX(GMI_WR_N_PI0, SPI4, NORMAL, NORMAL, INPUT), 164 165 /* PWM1 pinmux */ 166 DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), 167 168 /* SOC pinmux */ 169 DEFAULT_PINMUX(GMI_CS1_N_PJ2, SOC, NORMAL, TRISTATE, INPUT), 170 DEFAULT_PINMUX(GMI_OE_N_PI1, SOC, NORMAL, TRISTATE, INPUT), 171 172 /* EXTPERIPH2 pinmux */ 173 DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT), 174 175 /* SDMMC1 pinmux */ 176 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), 177 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), 178 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), 179 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), 180 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), 181 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), 182 183 /* SDMMC3 pinmux */ 184 DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), 185 DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), 186 DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), 187 DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), 188 DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), 189 DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), 190 DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT), 191 DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT), 192 193 /* SDMMC4 pinmux */ 194 DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT), 195 DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT), 196 DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT), 197 DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT), 198 DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT), 199 DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT), 200 DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT), 201 DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT), 202 DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT), 203 DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT), 204 205 /* BLINK pinmux */ 206 DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), 207 208 /* KBC pinmux */ 209 DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), 210 DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), 211 DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), 212 DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), 213 DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), 214 DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), 215 216 /*Audio Codec*/ 217 DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, OUTPUT), 218 DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD1, NORMAL, TRISTATE, OUTPUT), 219 DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), 220 DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT), 221 222 /* UARTA pinmux */ 223 DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, NORMAL, TRISTATE, INPUT), 224 DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT), 225 226 /* I2CPWR pinmux (I2C5) */ 227 I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 228 I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 229 230 /* SYSCLK pinmux */ 231 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), 232 233 /* RTCK pinmux */ 234 DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), 235 236 /* CLK pinmux */ 237 DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), 238 239 /* PWRON pinmux */ 240 DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), 241 242 /* CPU pinmux */ 243 DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), 244 245 /* PMI pinmux */ 246 DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), 247 248 /* RESET_OUT_N pinmux */ 249 DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), 250 251 /* EXTPERIPH3 pinmux */ 252 DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), 253 254 /* I2C1 pinmux */ 255 I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 256 I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 257 258 /* UARTB pinmux */ 259 DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT), 260 DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), 261 262 /* IRDA pinmux */ 263 DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT), 264 DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT), 265 266 /* UARTC pinmux */ 267 DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT), 268 DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), 269 DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT), 270 DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), 271 272 /* OWR pinmux */ 273 DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), 274 275 /* CEC pinmux */ 276 CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), 277 278 /* I2C4 pinmux */ 279 DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), 280 DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), 281 282 /* USB pinmux */ 283 USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), 284 285 /* nct */ 286 DEFAULT_PINMUX(GPIO_X6_AUD_PX6, SPI6, UP, TRISTATE, INPUT), 287 }; 288 289 static struct pmux_pingrp_config unused_pins_lowpower[] = { 290 DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT), 291 DEFAULT_PINMUX(USB_VBUS_EN1_PN5, RSVD3, DOWN, TRISTATE, OUTPUT), 292 }; 293 294 /* Initially setting all used GPIO's to non-TRISTATE */ 295 static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = { 296 DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT), 297 DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD1, UP, NORMAL, INPUT), 298 DEFAULT_PINMUX(GPIO_X6_AUD_PX6, RSVD3, UP, NORMAL, INPUT), 299 DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT), 300 DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT), 301 DEFAULT_PINMUX(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT), 302 DEFAULT_PINMUX(GPIO_X1_AUD_PX1, RSVD3, DOWN, NORMAL, INPUT), 303 DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT), 304 305 DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, DOWN, NORMAL, OUTPUT), 306 DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, OUTPUT), 307 DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT), 308 DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, NORMAL, OUTPUT), 309 DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT), 310 DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), 311 312 DEFAULT_PINMUX(PBB3, RSVD3, DOWN, NORMAL, OUTPUT), 313 DEFAULT_PINMUX(PBB5, RSVD3, DOWN, NORMAL, OUTPUT), 314 DEFAULT_PINMUX(PBB6, RSVD3, DOWN, NORMAL, OUTPUT), 315 DEFAULT_PINMUX(PBB7, RSVD3, DOWN, NORMAL, OUTPUT), 316 DEFAULT_PINMUX(PCC1, RSVD3, DOWN, NORMAL, INPUT), 317 DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT), 318 319 DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, NORMAL, OUTPUT), 320 DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, NORMAL, OUTPUT), 321 DEFAULT_PINMUX(GMI_AD10_PH2, GMI, DOWN, NORMAL, OUTPUT), 322 DEFAULT_PINMUX(GMI_AD11_PH3, GMI, DOWN, NORMAL, OUTPUT), 323 DEFAULT_PINMUX(GMI_AD12_PH4, GMI, UP, NORMAL, INPUT), 324 DEFAULT_PINMUX(GMI_AD13_PH5, GMI, DOWN, NORMAL, OUTPUT), 325 DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, NORMAL, INPUT), 326 DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, NORMAL, INPUT), 327 DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, OUTPUT), 328 DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, UP, NORMAL, INPUT), 329 DEFAULT_PINMUX(GMI_CLK_PK1, GMI, DOWN, NORMAL, OUTPUT), 330 DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, NORMAL, INPUT), 331 DEFAULT_PINMUX(GMI_CS2_N_PK3, GMI, UP, NORMAL, INPUT), 332 DEFAULT_PINMUX(GMI_CS3_N_PK4, GMI, UP, NORMAL, OUTPUT), 333 DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT), 334 DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), 335 DEFAULT_PINMUX(GMI_DQS_P_PJ3, GMI, UP, NORMAL, INPUT), 336 DEFAULT_PINMUX(GMI_IORDY_PI5, GMI, UP, NORMAL, INPUT), 337 DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT), 338 339 DEFAULT_PINMUX(SDMMC1_WP_N_PV3, SPI4, UP, NORMAL, OUTPUT), 340 DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT), 341 342 DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT), 343 DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT), 344 DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), 345 DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT), 346 DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT), 347 DEFAULT_PINMUX(KB_ROW3_PR3, KBC, DOWN, NORMAL, INPUT), 348 DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT), 349 DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT), 350 DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), 351 352 DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD3, NORMAL, NORMAL, OUTPUT), 353 DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, OUTPUT), 354 DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, INPUT), 355 DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT), 356 357 DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT), 358 359 DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), 360 DEFAULT_PINMUX(SPDIF_IN_PK6, USB, NORMAL, NORMAL, INPUT), 361 362 DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT), 363 }; 364 365 static struct pmux_drvgrp_config dalmore_padctrl[] = { 366 /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ 367 DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ 368 SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), 369 }; 370 #endif /* PINMUX_CONFIG_COMMON_H */ 371