1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/addrspace.h> 9 #include <asm/types.h> 10 #include <environment.h> 11 #include <spi.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #define MSCC_GPIO_ALT0 0x54 16 #define MSCC_GPIO_ALT1 0x58 17 18 void external_cs_manage(struct udevice *dev, bool enable) 19 { 20 u32 cs = spi_chip_select(dev); 21 /* IF_SI0_OWNER, select the owner of the SI interface 22 * Encoding: 0: SI Slave 23 * 1: SI Boot Master 24 * 2: SI Master Controller 25 */ 26 if (!enable) { 27 writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE | 28 ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE); 29 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, 30 ICPU_GENERAL_CTRL_IF_SI_OWNER_M, 31 ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); 32 } else { 33 writel(0, BASE_CFG + ICPU_SW_MODE); 34 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, 35 ICPU_GENERAL_CTRL_IF_SI_OWNER_M, 36 ICPU_GENERAL_CTRL_IF_SI_OWNER(1)); 37 } 38 } 39 40 void board_debug_uart_init(void) 41 { 42 /* too early for the pinctrl driver, so configure the UART pins here */ 43 setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7)); 44 clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7)); 45 } 46 47 int board_early_init_r(void) 48 { 49 /* Prepare SPI controller to be used in master mode */ 50 writel(0, BASE_CFG + ICPU_SW_MODE); 51 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, 52 ICPU_GENERAL_CTRL_IF_SI_OWNER_M, 53 ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); 54 55 /* Address of boot parameters */ 56 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; 57 return 0; 58 } 59