xref: /openbmc/u-boot/board/mscc/common/spi.c (revision 407b5b956a2e0facf6668fc8b295f4be9205c83e)
1  // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2  /*
3   * Copyright (c) 2018 Microsemi Coprporation
4   */
5  
6  #include <common.h>
7  #include <asm/io.h>
8  #include <spi.h>
9  
10  void external_cs_manage(struct udevice *dev, bool enable)
11  {
12  	u32 cs = spi_chip_select(dev);
13  	/* IF_SI0_OWNER, select the owner of the SI interface
14  	 * Encoding: 0: SI Slave
15  	 *	     1: SI Boot Master
16  	 *	     2: SI Master Controller
17  	 */
18  	if (!enable) {
19  		writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
20  		       ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
21  		       BASE_CFG + ICPU_SW_MODE);
22  		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
23  				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
24  				ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
25  	} else {
26  		writel(0, BASE_CFG + ICPU_SW_MODE);
27  		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
28  				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
29  				ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
30  	}
31  }
32