1/* 2 modified from SH-IPL+g 3 Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. 4 5 Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R 6 7 Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org> 8 9 * SPDX-License-Identifier: GPL-2.0+ 10*/ 11 12#include <config.h> 13#include <version.h> 14 15#include <asm/processor.h> 16#include <asm/macro.h> 17 18#ifdef CONFIG_CPU_SH7751 19#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ 20#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ 21#ifdef CONFIG_MARUBUN_PCCARD 22#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 23 A3:2 A2:15 A1:15 A0:6 A0B:7 */ 24#else /* CONFIG_MARUBUN_PCCARD */ 25#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 26 A3:2 A2:15 A1:15 A0:6 A0B:7 */ 27#endif /* CONFIG_MARUBUN_PCCARD */ 28#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 29 A2: 1-3 A1: 1-3 A0: 0-1 */ 30#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ 31#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ 32#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ 33#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ 34#else /* CONFIG_CPU_SH7751 */ 35#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ 36#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ 37#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 38 A3:2 A2:15 A1:15 A0:15 A0B:7 */ 39#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 40 A2: 1-3 A1: 1-3 A0: 0-1 */ 41#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ 42#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ 43#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ 44#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ 45#endif /* CONFIG_CPU_SH7751 */ 46 47 .global lowlevel_init 48 .text 49 .align 2 50 51lowlevel_init: 52 53 write32 CCR_A, CCR_D_DISABLE 54 55init_bsc: 56 write16 FRQCR_A, FRQCR_D 57 58 write32 BCR1_A, BCR1_D 59 60 write16 BCR2_A, BCR2_D 61 62 write32 WCR1_A, WCR1_D 63 64 write32 WCR2_A, WCR2_D 65 66 write32 WCR3_A, WCR3_D 67 68 write32 MCR_A, MCR_D1 69 70 /* Set SDRAM mode */ 71 write8 SDMR3_A, SDMR3_D 72 73 ! Do you need PCMCIA setting? 74 ! If so, please add the lines here... 75 76 write16 RTCNT_A, RTCNT_D 77 78 write16 RTCOR_A, RTCOR_D 79 80 write16 RTCSR_A, RTCSR_D 81 82 write16 RFCR_A, RFCR_D 83 84 /* Wait DRAM refresh 30 times */ 85 mov #30, r3 861: 87 mov.w @r1, r0 88 extu.w r0, r2 89 cmp/hi r3, r2 90 bf 1b 91 92 write32 MCR_A, MCR_D2 93 94 /* Set SDRAM mode */ 95 write8 SDMR3_A, SDMR3_D 96 97 rts 98 nop 99 100 .align 2 101 102CCR_A: .long CCR 103CCR_D_DISABLE: .long 0x0808 104FRQCR_A: .long FRQCR 105FRQCR_D: 106#ifdef CONFIG_CPU_TYPE_R 107 .word 0x0e1a /* 12:3:3 */ 108#else /* CONFIG_CPU_TYPE_R */ 109#ifdef CONFIG_GOOD_SESH4 110 .word 0x00e13 /* 6:2:1 */ 111#else 112 .word 0x00e23 /* 6:1:1 */ 113#endif 114.align 2 115#endif /* CONFIG_CPU_TYPE_R */ 116 117BCR1_A: .long BCR1 118BCR1_D: .long 0x00000008 /* Area 3 SDRAM */ 119BCR2_A: .long BCR2 120BCR2_D: .long BCR2_D_VALUE /* Bus width settings */ 121WCR1_A: .long WCR1 122WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ 123WCR2_A: .long WCR2 124WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ 125WCR3_A: .long WCR3 126WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ 127RTCSR_A: .long RTCSR 128RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ 129.align 2 130RTCNT_A: .long RTCNT 131RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ 132.align 2 133RTCOR_A: .long RTCOR 134RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ 135.align 2 136SDMR3_A: .long SDMR3_ADDRESS 137SDMR3_D: .long 0x00 138MCR_A: .long MCR 139MCR_D1: .long MCR_D1_VALUE 140MCR_D2: .long MCR_D2_VALUE 141RFCR_A: .long RFCR 142RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ 143.align 2 144