1/* 2 modified from SH-IPL+g 3 Renesaso SuperH Solution Enginge MS775x BSC setting 4 Coyright (c) 2007 Nobuhiro Iwamatsu 5*/ 6 7#include <config.h> 8#include <version.h> 9 10#include <asm/processor.h> 11 12#ifdef CONFIG_CPU_SUBTYPE_SH7751 13#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ 14#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ 15#ifdef CONFIG_MRSHPC 16#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 17 A3:2 A2:15 A1:15 A0:6 A0B:7 */ 18#else /* CONFIG_MRSHPC*/ 19#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 20 A3:2 A2:15 A1:15 A0:6 A0B:7 */ 21#endif /* CONFIG_MRSHPC */ 22#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 23 A2: 1-3 A1: 1-3 A0: 0-1 */ 24#define LED_ADDRESS 0xBA000000 /* Address of LED register */ 25#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ 26#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ 27#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */ 28#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ 29#define SWITCH_ADDR 0xB9000000 /* Address of DIP switches */ 30#else /* CONFIG_CPU_SUBTYPE_SH7751 */ 31#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ 32#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ 33#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 34 A3:2 A2:15 A1:15 A0:15 A0B:7 */ 35#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 36 A2: 1-3 A1: 1-3 A0: 0-1 */ 37#define LED_ADDRESS 0xB0C00000 /* Address of LED register */ 38#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ 39#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ 40#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */ 41#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ 42#define SWITCH_ADDR 0xb0800000 /* Address of DIP switches */ 43#endif /* CONFIG_CPU_SUBTYPE_SH7751 */ 44 45 .global lowlevel_init 46 .text 47 .align 2 48 49lowlevel_init: 50 51 mov.l L_CCR, r1 ! CCR Address 52 mov.l L_CCR_DISABLE, r0 ! CCR Data 53 mov.l r0, @r1 54 55init_bsc: 56 mov.l FRQCR_A,r1 /* FRQCR Address */ 57 mov.l FRQCR_D,r0 /* FRQCR Data */ 58 mov.w r0,@r1 59 60 mov.l BCR1_A,r1 /* BCR1 Address */ 61 mov.l BCR1_D,r0 /* BCR1 Data */ 62 mov.l r0,@r1 63 64 mov.l BCR2_A,r1 /* BCR2 Address */ 65 mov.l BCR2_D,r0 /* BCR2 Data */ 66 mov.w r0,@r1 67 68 mov.l WCR1_A,r1 /* WCR1 Address */ 69 mov.l WCR1_D,r0 /* WCR1 Data */ 70 mov.l r0,@r1 71 72 mov.l WCR2_A,r1 /* WCR2 Address */ 73 mov.l WCR2_D,r0 /* WCR2 Data */ 74 mov.l r0,@r1 75 76 mov.l WCR3_A,r1 /* WCR3 Address */ 77 mov.l WCR3_D,r0 /* WCR3 Data */ 78 mov.l r0,@r1 79 80 mov.l LED_A,r1 /* LED Address */ 81 mov #0xff,r0 /* LED ALL 'on' */ 82 shll8 r0 83 mov.w r0,@r1 84 85 mov.l MCR_A,r1 /* MCR Address */ 86 mov.l MCR_D1,r0 /* MCR Data1 */ 87 mov.l r0,@r1 88 89 mov.l SDMR3_A,r1 /* Set SDRAM mode */ 90 mov #0,r0 91 mov.b r0,@r1 92 93 ! Do you need PCMCIA setting? 94 ! If so, please add the lines here... 95 96 mov.l RTCNT_A,r1 /* RTCNT Address */ 97 mov.l RTCNT_D,r0 /* RTCNT Data */ 98 mov.w r0,@r1 99 100 mov.l RTCOR_A,r1 /* RTCOR Address */ 101 mov.l RTCOR_D,r0 /* RTCOR Data */ 102 mov.w r0,@r1 103 104 mov.l RTCSR_A,r1 /* RTCSR Address */ 105 mov.l RTCSR_D,r0 /* RTCSR Data */ 106 mov.w r0,@r1 107 108 mov.l RFCR_A,r1 /* RFCR Address */ 109 mov.l RFCR_D,r0 /* RFCR Data */ 110 mov.w r0,@r1 /* Clear reflesh counter */ 111 /* Wait DRAM refresh 30 times */ 112 mov #30,r3 1131: 114 mov.w @r1,r0 115 extu.w r0,r2 116 cmp/hi r3,r2 117 bf 1b 118 119 mov.l MCR_A,r1 /* MCR Address */ 120 mov.l MCR_D2,r0 /* MCR Data2 */ 121 mov.l r0,@r1 122 123 mov.l SDMR3_A,r1 /* Set SDRAM mode */ 124 mov #0,r0 125 mov.b r0,@r1 126 127 rts 128 nop 129 130 .align 2 131 132L_CCR: .long CCR 133L_CCR_DISABLE: .long 0x0808 134FRQCR_A: .long FRQCR 135FRQCR_D: 136#ifdef CONFIG_CPU_SUBTYPE_SH_R 137 .long 0x00000e1a /* 12:3:3 */ 138#else 139#ifdef CONFIG_GOOD_SESH4 140 .long 0x00000e13 /* 6:2:1 */ 141#else 142 .long 0x00000e23 /* 6:1:1 */ 143#endif 144#endif /* CONFIG_CPU_SUBTYPE_SH_R */ 145 146BCR1_A: .long BCR1 147BCR1_D: .long 0x00000008 /* Area 3 SDRAM */ 148BCR2_A: .long BCR2 149BCR2_D: .long BCR2_D_VALUE /* Bus width settings */ 150WCR1_A: .long WCR1 151WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ 152WCR2_A: .long WCR2 153WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ 154WCR3_A: .long WCR3 155WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ 156LED_A: .long LED_ADDRESS /* LED Address */ 157RTCSR_A: .long RTCSR 158RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ 159RTCNT_A: .long RTCNT 160RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ 161RTCOR_A: .long RTCOR 162RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ 163SDMR3_A: .long SDMR3_ADDRESS 164MCR_A: .long MCR 165MCR_D1: .long MCR_D1_VALUE 166MCR_D2: .long MCR_D2_VALUE 167RFCR_A: .long RFCR 168RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ 169 170