1/* 2 modified from SH-IPL+g 3 Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. 4 5 Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R 6 7 Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org> 8 9 * SPDX-License-Identifier: GPL-2.0+ 10*/ 11 12#include <config.h> 13 14#include <asm/processor.h> 15#include <asm/macro.h> 16 17#ifdef CONFIG_CPU_SH7751 18#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ 19#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ 20#ifdef CONFIG_MARUBUN_PCCARD 21#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 22 A3:2 A2:15 A1:15 A0:6 A0B:7 */ 23#else /* CONFIG_MARUBUN_PCCARD */ 24#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 25 A3:2 A2:15 A1:15 A0:6 A0B:7 */ 26#endif /* CONFIG_MARUBUN_PCCARD */ 27#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 28 A2: 1-3 A1: 1-3 A0: 0-1 */ 29#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ 30#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ 31#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ 32#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ 33#else /* CONFIG_CPU_SH7751 */ 34#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ 35#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ 36#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 37 A3:2 A2:15 A1:15 A0:15 A0B:7 */ 38#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 39 A2: 1-3 A1: 1-3 A0: 0-1 */ 40#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ 41#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ 42#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ 43#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ 44#endif /* CONFIG_CPU_SH7751 */ 45 46 .global lowlevel_init 47 .text 48 .align 2 49 50lowlevel_init: 51 52 write32 CCR_A, CCR_D_DISABLE 53 54init_bsc: 55 write16 FRQCR_A, FRQCR_D 56 57 write32 BCR1_A, BCR1_D 58 59 write16 BCR2_A, BCR2_D 60 61 write32 WCR1_A, WCR1_D 62 63 write32 WCR2_A, WCR2_D 64 65 write32 WCR3_A, WCR3_D 66 67 write32 MCR_A, MCR_D1 68 69 /* Set SDRAM mode */ 70 write8 SDMR3_A, SDMR3_D 71 72 ! Do you need PCMCIA setting? 73 ! If so, please add the lines here... 74 75 write16 RTCNT_A, RTCNT_D 76 77 write16 RTCOR_A, RTCOR_D 78 79 write16 RTCSR_A, RTCSR_D 80 81 write16 RFCR_A, RFCR_D 82 83 /* Wait DRAM refresh 30 times */ 84 mov #30, r3 851: 86 mov.w @r1, r0 87 extu.w r0, r2 88 cmp/hi r3, r2 89 bf 1b 90 91 write32 MCR_A, MCR_D2 92 93 /* Set SDRAM mode */ 94 write8 SDMR3_A, SDMR3_D 95 96 rts 97 nop 98 99 .align 2 100 101CCR_A: .long CCR 102CCR_D_DISABLE: .long 0x0808 103FRQCR_A: .long FRQCR 104FRQCR_D: 105#ifdef CONFIG_CPU_TYPE_R 106 .word 0x0e1a /* 12:3:3 */ 107#else /* CONFIG_CPU_TYPE_R */ 108#ifdef CONFIG_GOOD_SESH4 109 .word 0x00e13 /* 6:2:1 */ 110#else 111 .word 0x00e23 /* 6:1:1 */ 112#endif 113.align 2 114#endif /* CONFIG_CPU_TYPE_R */ 115 116BCR1_A: .long BCR1 117BCR1_D: .long 0x00000008 /* Area 3 SDRAM */ 118BCR2_A: .long BCR2 119BCR2_D: .long BCR2_D_VALUE /* Bus width settings */ 120WCR1_A: .long WCR1 121WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ 122WCR2_A: .long WCR2 123WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ 124WCR3_A: .long WCR3 125WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ 126RTCSR_A: .long RTCSR 127RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ 128.align 2 129RTCNT_A: .long RTCNT 130RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ 131.align 2 132RTCOR_A: .long RTCOR 133RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ 134.align 2 135SDMR3_A: .long SDMR3_ADDRESS 136SDMR3_D: .long 0x00 137MCR_A: .long MCR 138MCR_D1: .long MCR_D1_VALUE 139MCR_D2: .long MCR_D2_VALUE 140RFCR_A: .long RFCR 141RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ 142.align 2 143