169df3c4dSNobuhiro Iwamatsu/* 269df3c4dSNobuhiro Iwamatsu modified from SH-IPL+g 3047375bfSNobuhiro Iwamatsu Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. 4047375bfSNobuhiro Iwamatsu 5047375bfSNobuhiro Iwamatsu Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R 6047375bfSNobuhiro Iwamatsu 7047375bfSNobuhiro Iwamatsu Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org> 8047375bfSNobuhiro Iwamatsu 9047375bfSNobuhiro Iwamatsu * See file CREDITS for list of people who contributed to this 10047375bfSNobuhiro Iwamatsu * project. 11047375bfSNobuhiro Iwamatsu * 12047375bfSNobuhiro Iwamatsu * This program is free software; you can redistribute it and/or 13047375bfSNobuhiro Iwamatsu * modify it under the terms of the GNU General Public License as 14047375bfSNobuhiro Iwamatsu * published by the Free Software Foundation; either version 2 of 15047375bfSNobuhiro Iwamatsu * the License, or (at your option) any later version. 16047375bfSNobuhiro Iwamatsu * 17047375bfSNobuhiro Iwamatsu * This program is distributed in the hope that it will be useful, 18047375bfSNobuhiro Iwamatsu * but WITHOUT ANY WARRANTY; without even the implied warranty of 19047375bfSNobuhiro Iwamatsu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20047375bfSNobuhiro Iwamatsu * GNU General Public License for more details. 21047375bfSNobuhiro Iwamatsu * 22047375bfSNobuhiro Iwamatsu * You should have received a copy of the GNU General Public License 23047375bfSNobuhiro Iwamatsu * along with this program; if not, write to the Free Software 24047375bfSNobuhiro Iwamatsu * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25047375bfSNobuhiro Iwamatsu * MA 02111-1307 USA 2669df3c4dSNobuhiro Iwamatsu*/ 2769df3c4dSNobuhiro Iwamatsu 2869df3c4dSNobuhiro Iwamatsu#include <config.h> 2969df3c4dSNobuhiro Iwamatsu#include <version.h> 3069df3c4dSNobuhiro Iwamatsu 3169df3c4dSNobuhiro Iwamatsu#include <asm/processor.h> 32f7e78f3bSJean-Christophe PLAGNIOL-VILLARD#include <asm/macro.h> 3369df3c4dSNobuhiro Iwamatsu 34047375bfSNobuhiro Iwamatsu#ifdef CONFIG_CPU_SH7751 3569df3c4dSNobuhiro Iwamatsu#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ 3669df3c4dSNobuhiro Iwamatsu#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ 37047375bfSNobuhiro Iwamatsu#ifdef CONFIG_MARUBUN_PCCARD 3869df3c4dSNobuhiro Iwamatsu#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 3969df3c4dSNobuhiro Iwamatsu A3:2 A2:15 A1:15 A0:6 A0B:7 */ 40047375bfSNobuhiro Iwamatsu#else /* CONFIG_MARUBUN_PCCARD */ 4169df3c4dSNobuhiro Iwamatsu#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 4269df3c4dSNobuhiro Iwamatsu A3:2 A2:15 A1:15 A0:6 A0B:7 */ 43047375bfSNobuhiro Iwamatsu#endif /* CONFIG_MARUBUN_PCCARD */ 4469df3c4dSNobuhiro Iwamatsu#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 4569df3c4dSNobuhiro Iwamatsu A2: 1-3 A1: 1-3 A0: 0-1 */ 4669df3c4dSNobuhiro Iwamatsu#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ 4769df3c4dSNobuhiro Iwamatsu#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ 48e4430779SJean-Christophe PLAGNIOL-VILLARD#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ 4969df3c4dSNobuhiro Iwamatsu#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ 50047375bfSNobuhiro Iwamatsu#else /* CONFIG_CPU_SH7751 */ 5169df3c4dSNobuhiro Iwamatsu#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ 5269df3c4dSNobuhiro Iwamatsu#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ 5369df3c4dSNobuhiro Iwamatsu#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 5469df3c4dSNobuhiro Iwamatsu A3:2 A2:15 A1:15 A0:15 A0B:7 */ 5569df3c4dSNobuhiro Iwamatsu#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 5669df3c4dSNobuhiro Iwamatsu A2: 1-3 A1: 1-3 A0: 0-1 */ 5769df3c4dSNobuhiro Iwamatsu#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ 5869df3c4dSNobuhiro Iwamatsu#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ 59e4430779SJean-Christophe PLAGNIOL-VILLARD#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ 6069df3c4dSNobuhiro Iwamatsu#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ 61047375bfSNobuhiro Iwamatsu#endif /* CONFIG_CPU_SH7751 */ 6269df3c4dSNobuhiro Iwamatsu 6369df3c4dSNobuhiro Iwamatsu .global lowlevel_init 6469df3c4dSNobuhiro Iwamatsu .text 6569df3c4dSNobuhiro Iwamatsu .align 2 6669df3c4dSNobuhiro Iwamatsu 6769df3c4dSNobuhiro Iwamatsulowlevel_init: 6869df3c4dSNobuhiro Iwamatsu 69f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 CCR_A, CCR_D_DISABLE 7069df3c4dSNobuhiro Iwamatsu 7169df3c4dSNobuhiro Iwamatsuinit_bsc: 72f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 FRQCR_A, FRQCR_D 7369df3c4dSNobuhiro Iwamatsu 74f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 BCR1_A, BCR1_D 7569df3c4dSNobuhiro Iwamatsu 76f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 BCR2_A, BCR2_D 7769df3c4dSNobuhiro Iwamatsu 78f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 WCR1_A, WCR1_D 7969df3c4dSNobuhiro Iwamatsu 80f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 WCR2_A, WCR2_D 8169df3c4dSNobuhiro Iwamatsu 82f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 WCR3_A, WCR3_D 8369df3c4dSNobuhiro Iwamatsu 84f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 MCR_A, MCR_D1 8569df3c4dSNobuhiro Iwamatsu 86f7e78f3bSJean-Christophe PLAGNIOL-VILLARD /* Set SDRAM mode */ 87*c9935c99SNobuhiro Iwamatsu write8 SDMR3_A, SDMR3_D 8869df3c4dSNobuhiro Iwamatsu 8969df3c4dSNobuhiro Iwamatsu ! Do you need PCMCIA setting? 9069df3c4dSNobuhiro Iwamatsu ! If so, please add the lines here... 9169df3c4dSNobuhiro Iwamatsu 92f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 RTCNT_A, RTCNT_D 9369df3c4dSNobuhiro Iwamatsu 94f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 RTCOR_A, RTCOR_D 9569df3c4dSNobuhiro Iwamatsu 96f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 RTCSR_A, RTCSR_D 9769df3c4dSNobuhiro Iwamatsu 98f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 RFCR_A, RFCR_D 99f7e78f3bSJean-Christophe PLAGNIOL-VILLARD 10069df3c4dSNobuhiro Iwamatsu /* Wait DRAM refresh 30 times */ 10169df3c4dSNobuhiro Iwamatsu mov #30, r3 10269df3c4dSNobuhiro Iwamatsu1: 10369df3c4dSNobuhiro Iwamatsu mov.w @r1, r0 10469df3c4dSNobuhiro Iwamatsu extu.w r0, r2 10569df3c4dSNobuhiro Iwamatsu cmp/hi r3, r2 10669df3c4dSNobuhiro Iwamatsu bf 1b 10769df3c4dSNobuhiro Iwamatsu 108f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 MCR_A, MCR_D2 10969df3c4dSNobuhiro Iwamatsu 110f7e78f3bSJean-Christophe PLAGNIOL-VILLARD /* Set SDRAM mode */ 111*c9935c99SNobuhiro Iwamatsu write8 SDMR3_A, SDMR3_D 11269df3c4dSNobuhiro Iwamatsu 11369df3c4dSNobuhiro Iwamatsu rts 11469df3c4dSNobuhiro Iwamatsu nop 11569df3c4dSNobuhiro Iwamatsu 11669df3c4dSNobuhiro Iwamatsu .align 2 11769df3c4dSNobuhiro Iwamatsu 118047375bfSNobuhiro IwamatsuCCR_A: .long CCR 119047375bfSNobuhiro IwamatsuCCR_D_DISABLE: .long 0x0808 12069df3c4dSNobuhiro IwamatsuFRQCR_A: .long FRQCR 12169df3c4dSNobuhiro IwamatsuFRQCR_D: 122047375bfSNobuhiro Iwamatsu#ifdef CONFIG_CPU_TYPE_R 12369df3c4dSNobuhiro Iwamatsu .long 0x00000e1a /* 12:3:3 */ 124047375bfSNobuhiro Iwamatsu#else /* CONFIG_CPU_TYPE_R */ 12569df3c4dSNobuhiro Iwamatsu#ifdef CONFIG_GOOD_SESH4 12669df3c4dSNobuhiro Iwamatsu .long 0x00000e13 /* 6:2:1 */ 12769df3c4dSNobuhiro Iwamatsu#else 12869df3c4dSNobuhiro Iwamatsu .long 0x00000e23 /* 6:1:1 */ 12969df3c4dSNobuhiro Iwamatsu#endif 130047375bfSNobuhiro Iwamatsu#endif /* CONFIG_CPU_TYPE_R */ 13169df3c4dSNobuhiro Iwamatsu 13269df3c4dSNobuhiro IwamatsuBCR1_A: .long BCR1 13369df3c4dSNobuhiro IwamatsuBCR1_D: .long 0x00000008 /* Area 3 SDRAM */ 13469df3c4dSNobuhiro IwamatsuBCR2_A: .long BCR2 13569df3c4dSNobuhiro IwamatsuBCR2_D: .long BCR2_D_VALUE /* Bus width settings */ 13669df3c4dSNobuhiro IwamatsuWCR1_A: .long WCR1 13769df3c4dSNobuhiro IwamatsuWCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ 13869df3c4dSNobuhiro IwamatsuWCR2_A: .long WCR2 13969df3c4dSNobuhiro IwamatsuWCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ 14069df3c4dSNobuhiro IwamatsuWCR3_A: .long WCR3 14169df3c4dSNobuhiro IwamatsuWCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ 14269df3c4dSNobuhiro IwamatsuRTCSR_A: .long RTCSR 14369df3c4dSNobuhiro IwamatsuRTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ 14469df3c4dSNobuhiro IwamatsuRTCNT_A: .long RTCNT 14569df3c4dSNobuhiro IwamatsuRTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ 14669df3c4dSNobuhiro IwamatsuRTCOR_A: .long RTCOR 14769df3c4dSNobuhiro IwamatsuRTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ 14869df3c4dSNobuhiro IwamatsuSDMR3_A: .long SDMR3_ADDRESS 149*c9935c99SNobuhiro IwamatsuSDMR3_D: .long 0x00 15069df3c4dSNobuhiro IwamatsuMCR_A: .long MCR 15169df3c4dSNobuhiro IwamatsuMCR_D1: .long MCR_D1_VALUE 15269df3c4dSNobuhiro IwamatsuMCR_D2: .long MCR_D2_VALUE 15369df3c4dSNobuhiro IwamatsuRFCR_A: .long RFCR 15469df3c4dSNobuhiro IwamatsuRFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ 155