1/*
2 * Copyright (C) 2007
3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 *
5 * Copyright (C) 2007
6 * Kenati Technologies, Inc.
7 *
8 * board/ms7722se/lowlevel_init.S
9 *
10 * SPDX-License-Identifier:	GPL-2.0+
11 */
12
13#include <config.h>
14
15#include <asm/processor.h>
16#include <asm/macro.h>
17
18/*
19 * Board specific low level init code, called _very_ early in the
20 * startup sequence. Relocation to SDRAM has not happened yet, no
21 * stack is available, bss section has not been initialised, etc.
22 *
23 * (Note: As no stack is available, no subroutines can be called...).
24 */
25
26	.global	lowlevel_init
27
28	.text
29	.align	2
30
31lowlevel_init:
32
33	/*
34	 * Cache Control Register
35	 * Instruction Cache Invalidate
36	 */
37	write32	CCR_A, CCR_D
38
39	/*
40	 * Address of MMU Control Register
41	 * TI == TLB Invalidate bit
42	 */
43	write32	MMUCR_A, MMUCR_D
44
45	/* Address of Power Control Register 0 */
46	write32	MSTPCR0_A, MSTPCR0_D
47
48	/* Address of Power Control Register 2 */
49	write32	MSTPCR2_A, MSTPCR2_D
50
51	write16	SBSCR_A, SBSCR_D
52
53	write16	PSCR_A, PSCR_D
54
55	/* 0xA4520004 (Watchdog Control / Status Register) */
56!	write16	RWTCSR_A, RWTCSR_D_1	/* 0xA507 -> timer_STOP/WDT_CLK=max */
57
58	/* 0xA4520000 (Watchdog Count Register) */
59	write16	RWTCNT_A, RWTCNT_D	/*0x5A00 -> Clear */
60
61	/* 0xA4520004 (Watchdog Control / Status Register) */
62	write16	RWTCSR_A, RWTCSR_D_2	/* 0xA504 -> timer_STOP/CLK=500ms */
63
64	/* 0xA4150000 Frequency control register */
65	write32	FRQCR_A, FRQCR_D
66
67	write32	CCR_A, CCR_D_2
68
69bsc_init:
70
71	write16	PSELA_A, PSELA_D
72
73	write16	DRVCR_A, DRVCR_D
74
75	write16	PCCR_A, PCCR_D
76
77	write16	PECR_A, PECR_D
78
79	write16	PJCR_A, PJCR_D
80
81	write16	PXCR_A, PXCR_D
82
83	write32	CMNCR_A, CMNCR_D
84
85	write32	CS0BCR_A, CS0BCR_D
86
87	write32	CS2BCR_A, CS2BCR_D
88
89	write32	CS4BCR_A, CS4BCR_D
90
91	write32	CS5ABCR_A, CS5ABCR_D
92
93	write32	CS5BBCR_A, CS5BBCR_D
94
95	write32	CS6ABCR_A, CS6ABCR_D
96
97	write32	CS0WCR_A, CS0WCR_D
98
99	write32	CS2WCR_A, CS2WCR_D
100
101	write32	CS4WCR_A, CS4WCR_D
102
103	write32	CS5AWCR_A, CS5AWCR_D
104
105	write32	CS5BWCR_A, CS5BWCR_D
106
107	write32	CS6AWCR_A, CS6AWCR_D
108
109	! SDRAM initialization
110	write32	SDCR_A, SDCR_D
111
112	write32	SDWCR_A, SDWCR_D
113
114	write32	SDPCR_A, SDPCR_D
115
116	write32	RTCOR_A, RTCOR_D
117
118	write32	RTCSR_A, RTCSR_D
119
120	write8	SDMR3_A, SDMR3_D
121
122	! BL bit off (init = ON) (?!?)
123
124	stc	sr, r0				! BL bit off(init=ON)
125	mov.l	SR_MASK_D, r1
126	and	r1, r0
127	ldc	r0, sr
128
129	rts
130	mov	#0, r0
131
132	.align	2
133
134CCR_A:		.long	CCR
135MMUCR_A:	.long	MMUCR
136MSTPCR0_A:	.long	MSTPCR0
137MSTPCR2_A:	.long	MSTPCR2
138SBSCR_A:	.long	SBSCR
139PSCR_A:		.long	PSCR
140RWTCSR_A:	.long	RWTCSR
141RWTCNT_A:	.long	RWTCNT
142FRQCR_A:	.long	FRQCR
143
144CCR_D:		.long	0x00000800
145CCR_D_2:	.long	0x00000103
146MMUCR_D:	.long	0x00000004
147MSTPCR0_D:	.long	0x00001001
148MSTPCR2_D:	.long	0xffffffff
149FRQCR_D:	.long	0x07022538
150
151PSELA_A:	.long	0xa405014E
152PSELA_D:	.word	0x0A10
153	.align 2
154
155DRVCR_A:	.long	0xa405018A
156DRVCR_D:	.word	0x0554
157	.align 2
158
159PCCR_A:		.long	0xa4050104
160PCCR_D:		.word	0x8800
161	.align 2
162
163PECR_A:		.long	0xa4050108
164PECR_D:		.word	0x0000
165	.align 2
166
167PJCR_A:		.long	0xa4050110
168PJCR_D:		.word	0x1000
169	.align 2
170
171PXCR_A:		.long	0xa4050148
172PXCR_D:		.word	0x0AAA
173	.align 2
174
175CMNCR_A:	.long	CMNCR
176CMNCR_D:	.long	0x00000013
177CS0BCR_A:	.long	CS0BCR		! Flash bank 1
178CS0BCR_D:	.long	0x24920400
179CS2BCR_A:	.long	CS2BCR		! SRAM
180CS2BCR_D:	.long	0x24920400
181CS4BCR_A:	.long	CS4BCR		! FPGA, PCMCIA, USB, ext slot
182CS4BCR_D:	.long	0x24920400
183CS5ABCR_A:	.long	CS5ABCR		! Ext slot
184CS5ABCR_D:	.long	0x24920400
185CS5BBCR_A:	.long	CS5BBCR		! USB controller
186CS5BBCR_D:	.long	0x24920400
187CS6ABCR_A:	.long	CS6ABCR		! Ethernet
188CS6ABCR_D:	.long	0x24920400
189
190CS0WCR_A:	.long	CS0WCR
191CS0WCR_D:	.long	0x00000300
192CS2WCR_A:	.long	CS2WCR
193CS2WCR_D:	.long	0x00000300
194CS4WCR_A:	.long	CS4WCR
195CS4WCR_D:	.long	0x00000300
196CS5AWCR_A:	.long	CS5AWCR
197CS5AWCR_D:	.long	0x00000300
198CS5BWCR_A:	.long	CS5BWCR
199CS5BWCR_D:	.long	0x00000300
200CS6AWCR_A:	.long	CS6AWCR
201CS6AWCR_D:	.long	0x00000300
202
203SDCR_A:		.long	SBSC_SDCR
204SDCR_D:		.long	0x00020809
205SDWCR_A:	.long	SBSC_SDWCR
206SDWCR_D:	.long	0x00164d0d
207SDPCR_A:	.long	SBSC_SDPCR
208SDPCR_D:	.long	0x00000087
209RTCOR_A:	.long	SBSC_RTCOR
210RTCOR_D:	.long	0xA55A0034
211RTCSR_A:	.long	SBSC_RTCSR
212RTCSR_D:	.long	0xA55A0010
213SDMR3_A:	.long	0xFE500180
214SDMR3_D:	.long	0x0
215
216	.align	1
217
218SBSCR_D:	.word	0x0040
219PSCR_D:		.word	0x0000
220RWTCSR_D_1:	.word	0xA507
221RWTCSR_D_2:	.word	0xA507
222RWTCNT_D:	.word	0x5A00
223	.align	2
224
225SR_MASK_D:	.long	0xEFFFFF0F
226