1/*
2 * Copyright (C) 2007
3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 *
5 * Copyright (C) 2007
6 * Kenati Technologies, Inc.
7 *
8 * board/ms7722se/lowlevel_init.S
9 *
10 * SPDX-License-Identifier:	GPL-2.0+
11 */
12
13#include <config.h>
14#include <version.h>
15
16#include <asm/processor.h>
17#include <asm/macro.h>
18
19/*
20 * Board specific low level init code, called _very_ early in the
21 * startup sequence. Relocation to SDRAM has not happened yet, no
22 * stack is available, bss section has not been initialised, etc.
23 *
24 * (Note: As no stack is available, no subroutines can be called...).
25 */
26
27	.global	lowlevel_init
28
29	.text
30	.align	2
31
32lowlevel_init:
33
34	/*
35	 * Cache Control Register
36	 * Instruction Cache Invalidate
37	 */
38	write32	CCR_A, CCR_D
39
40	/*
41	 * Address of MMU Control Register
42	 * TI == TLB Invalidate bit
43	 */
44	write32	MMUCR_A, MMUCR_D
45
46	/* Address of Power Control Register 0 */
47	write32	MSTPCR0_A, MSTPCR0_D
48
49	/* Address of Power Control Register 2 */
50	write32	MSTPCR2_A, MSTPCR2_D
51
52	write16	SBSCR_A, SBSCR_D
53
54	write16	PSCR_A, PSCR_D
55
56	/* 0xA4520004 (Watchdog Control / Status Register) */
57!	write16	RWTCSR_A, RWTCSR_D_1	/* 0xA507 -> timer_STOP/WDT_CLK=max */
58
59	/* 0xA4520000 (Watchdog Count Register) */
60	write16	RWTCNT_A, RWTCNT_D	/*0x5A00 -> Clear */
61
62	/* 0xA4520004 (Watchdog Control / Status Register) */
63	write16	RWTCSR_A, RWTCSR_D_2	/* 0xA504 -> timer_STOP/CLK=500ms */
64
65	/* 0xA4150000 Frequency control register */
66	write32	FRQCR_A, FRQCR_D
67
68	write32	CCR_A, CCR_D_2
69
70bsc_init:
71
72	write16	PSELA_A, PSELA_D
73
74	write16	DRVCR_A, DRVCR_D
75
76	write16	PCCR_A, PCCR_D
77
78	write16	PECR_A, PECR_D
79
80	write16	PJCR_A, PJCR_D
81
82	write16	PXCR_A, PXCR_D
83
84	write32	CMNCR_A, CMNCR_D
85
86	write32	CS0BCR_A, CS0BCR_D
87
88	write32	CS2BCR_A, CS2BCR_D
89
90	write32	CS4BCR_A, CS4BCR_D
91
92	write32	CS5ABCR_A, CS5ABCR_D
93
94	write32	CS5BBCR_A, CS5BBCR_D
95
96	write32	CS6ABCR_A, CS6ABCR_D
97
98	write32	CS0WCR_A, CS0WCR_D
99
100	write32	CS2WCR_A, CS2WCR_D
101
102	write32	CS4WCR_A, CS4WCR_D
103
104	write32	CS5AWCR_A, CS5AWCR_D
105
106	write32	CS5BWCR_A, CS5BWCR_D
107
108	write32	CS6AWCR_A, CS6AWCR_D
109
110	! SDRAM initialization
111	write32	SDCR_A, SDCR_D
112
113	write32	SDWCR_A, SDWCR_D
114
115	write32	SDPCR_A, SDPCR_D
116
117	write32	RTCOR_A, RTCOR_D
118
119	write32	RTCSR_A, RTCSR_D
120
121	write8	SDMR3_A, SDMR3_D
122
123	! BL bit off (init = ON) (?!?)
124
125	stc	sr, r0				! BL bit off(init=ON)
126	mov.l	SR_MASK_D, r1
127	and	r1, r0
128	ldc	r0, sr
129
130	rts
131	mov	#0, r0
132
133	.align	2
134
135CCR_A:		.long	CCR
136MMUCR_A:	.long	MMUCR
137MSTPCR0_A:	.long	MSTPCR0
138MSTPCR2_A:	.long	MSTPCR2
139SBSCR_A:	.long	SBSCR
140PSCR_A:		.long	PSCR
141RWTCSR_A:	.long	RWTCSR
142RWTCNT_A:	.long	RWTCNT
143FRQCR_A:	.long	FRQCR
144
145CCR_D:		.long	0x00000800
146CCR_D_2:	.long	0x00000103
147MMUCR_D:	.long	0x00000004
148MSTPCR0_D:	.long	0x00001001
149MSTPCR2_D:	.long	0xffffffff
150FRQCR_D:	.long	0x07022538
151
152PSELA_A:	.long	0xa405014E
153PSELA_D:	.word	0x0A10
154	.align 2
155
156DRVCR_A:	.long	0xa405018A
157DRVCR_D:	.word	0x0554
158	.align 2
159
160PCCR_A:		.long	0xa4050104
161PCCR_D:		.word	0x8800
162	.align 2
163
164PECR_A:		.long	0xa4050108
165PECR_D:		.word	0x0000
166	.align 2
167
168PJCR_A:		.long	0xa4050110
169PJCR_D:		.word	0x1000
170	.align 2
171
172PXCR_A:		.long	0xa4050148
173PXCR_D:		.word	0x0AAA
174	.align 2
175
176CMNCR_A:	.long	CMNCR
177CMNCR_D:	.long	0x00000013
178CS0BCR_A:	.long	CS0BCR		! Flash bank 1
179CS0BCR_D:	.long	0x24920400
180CS2BCR_A:	.long	CS2BCR		! SRAM
181CS2BCR_D:	.long	0x24920400
182CS4BCR_A:	.long	CS4BCR		! FPGA, PCMCIA, USB, ext slot
183CS4BCR_D:	.long	0x24920400
184CS5ABCR_A:	.long	CS5ABCR		! Ext slot
185CS5ABCR_D:	.long	0x24920400
186CS5BBCR_A:	.long	CS5BBCR		! USB controller
187CS5BBCR_D:	.long	0x24920400
188CS6ABCR_A:	.long	CS6ABCR		! Ethernet
189CS6ABCR_D:	.long	0x24920400
190
191CS0WCR_A:	.long	CS0WCR
192CS0WCR_D:	.long	0x00000300
193CS2WCR_A:	.long	CS2WCR
194CS2WCR_D:	.long	0x00000300
195CS4WCR_A:	.long	CS4WCR
196CS4WCR_D:	.long	0x00000300
197CS5AWCR_A:	.long	CS5AWCR
198CS5AWCR_D:	.long	0x00000300
199CS5BWCR_A:	.long	CS5BWCR
200CS5BWCR_D:	.long	0x00000300
201CS6AWCR_A:	.long	CS6AWCR
202CS6AWCR_D:	.long	0x00000300
203
204SDCR_A:		.long	SBSC_SDCR
205SDCR_D:		.long	0x00020809
206SDWCR_A:	.long	SBSC_SDWCR
207SDWCR_D:	.long	0x00164d0d
208SDPCR_A:	.long	SBSC_SDPCR
209SDPCR_D:	.long	0x00000087
210RTCOR_A:	.long	SBSC_RTCOR
211RTCOR_D:	.long	0xA55A0034
212RTCSR_A:	.long	SBSC_RTCSR
213RTCSR_D:	.long	0xA55A0010
214SDMR3_A:	.long	0xFE500180
215SDMR3_D:	.long	0x0
216
217	.align	1
218
219SBSCR_D:	.word	0x0040
220PSCR_D:		.word	0x0000
221RWTCSR_D_1:	.word	0xA507
222RWTCSR_D_2:	.word	0xA507
223RWTCNT_D:	.word	0x5A00
224	.align	2
225
226SR_MASK_D:	.long	0xEFFFFF0F
227