1/*
2 * Copyright (C) 2007
3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 *
5 * Copyright (C) 2007
6 * Kenati Technologies, Inc.
7 *
8 * board/ms7722se/lowlevel_init.S
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <version.h>
28
29#include <asm/processor.h>
30#include <asm/macro.h>
31
32/*
33 * Board specific low level init code, called _very_ early in the
34 * startup sequence. Relocation to SDRAM has not happened yet, no
35 * stack is available, bss section has not been initialised, etc.
36 *
37 * (Note: As no stack is available, no subroutines can be called...).
38 */
39
40	.global	lowlevel_init
41
42	.text
43	.align	2
44
45lowlevel_init:
46
47	/*
48	 * Cache Control Register
49	 * Instruction Cache Invalidate
50	 */
51	write32	CCR_A, CCR_D
52
53	/*
54	 * Address of MMU Control Register
55	 * TI == TLB Invalidate bit
56	 */
57	write32	MMUCR_A, MMUCR_D
58
59	/* Address of Power Control Register 0 */
60	write32	MSTPCR0_A, MSTPCR0_D
61
62	/* Address of Power Control Register 2 */
63	write32	MSTPCR2_A, MSTPCR2_D
64
65	write16	SBSCR_A, SBSCR_D
66
67	write16	PSCR_A, PSCR_D
68
69	/* 0xA4520004 (Watchdog Control / Status Register) */
70!	write16	RWTCSR_A, RWTCSR_D_1	/* 0xA507 -> timer_STOP/WDT_CLK=max */
71
72	/* 0xA4520000 (Watchdog Count Register) */
73	write16	RWTCNT_A, RWTCNT_D	/*0x5A00 -> Clear */
74
75	/* 0xA4520004 (Watchdog Control / Status Register) */
76	write16	RWTCSR_A, RWTCSR_D_2	/* 0xA504 -> timer_STOP/CLK=500ms */
77
78	/* 0xA4150000 Frequency control register */
79	write32	FRQCR_A, FRQCR_D
80
81	write32	CCR_A, CCR_D_2
82
83bsc_init:
84
85	write16	PSELA_A, PSELA_D
86
87	write16	DRVCR_A, DRVCR_D
88
89	write16	PCCR_A, PCCR_D
90
91	write16	PECR_A, PECR_D
92
93	write16	PJCR_A, PJCR_D
94
95	write16	PXCR_A, PXCR_D
96
97	write32	CMNCR_A, CMNCR_D
98
99	write32	CS0BCR_A, CS0BCR_D
100
101	write32	CS2BCR_A, CS2BCR_D
102
103	write32	CS4BCR_A, CS4BCR_D
104
105	write32	CS5ABCR_A, CS5ABCR_D
106
107	write32	CS5BBCR_A, CS5BBCR_D
108
109	write32	CS6ABCR_A, CS6ABCR_D
110
111	write32	CS0WCR_A, CS0WCR_D
112
113	write32	CS2WCR_A, CS2WCR_D
114
115	write32	CS4WCR_A, CS4WCR_D
116
117	write32	CS5AWCR_A, CS5AWCR_D
118
119	write32	CS5BWCR_A, CS5BWCR_D
120
121	write32	CS6AWCR_A, CS6AWCR_D
122
123	! SDRAM initialization
124	write32	SDCR_A, SDCR_D
125
126	write32	SDWCR_A, SDWCR_D
127
128	write32	SDPCR_A, SDPCR_D
129
130	write32	RTCOR_A, RTCOR_D
131
132	write32	RTCSR_A, RTCSR_D
133
134	write8	SDMR3_A, SDMR3_D
135
136	! BL bit off (init = ON) (?!?)
137
138	stc	sr, r0				! BL bit off(init=ON)
139	mov.l	SR_MASK_D, r1
140	and	r1, r0
141	ldc	r0, sr
142
143	rts
144	mov	#0, r0
145
146	.align	2
147
148CCR_A:		.long	CCR
149MMUCR_A:	.long	MMUCR
150MSTPCR0_A:	.long	MSTPCR0
151MSTPCR2_A:	.long	MSTPCR2
152SBSCR_A:	.long	SBSCR
153PSCR_A:		.long	PSCR
154RWTCSR_A:	.long	RWTCSR
155RWTCNT_A:	.long	RWTCNT
156FRQCR_A:	.long	FRQCR
157
158CCR_D:		.long	0x00000800
159CCR_D_2:	.long	0x00000103
160MMUCR_D:	.long	0x00000004
161MSTPCR0_D:	.long	0x00001001
162MSTPCR2_D:	.long	0xffffffff
163FRQCR_D:	.long	0x07022538
164
165PSELA_A:	.long	0xa405014E
166PSELA_D:	.word	0x0A10
167	.align 2
168
169DRVCR_A:	.long	0xa405018A
170DRVCR_D:	.word	0x0554
171	.align 2
172
173PCCR_A:		.long	0xa4050104
174PCCR_D:		.word	0x8800
175	.align 2
176
177PECR_A:		.long	0xa4050108
178PECR_D:		.word	0x0000
179	.align 2
180
181PJCR_A:		.long	0xa4050110
182PJCR_D:		.word	0x1000
183	.align 2
184
185PXCR_A:		.long	0xa4050148
186PXCR_D:		.word	0x0AAA
187	.align 2
188
189CMNCR_A:	.long	CMNCR
190CMNCR_D:	.long	0x00000013
191CS0BCR_A:	.long	CS0BCR		! Flash bank 1
192CS0BCR_D:	.long	0x24920400
193CS2BCR_A:	.long	CS2BCR		! SRAM
194CS2BCR_D:	.long	0x24920400
195CS4BCR_A:	.long	CS4BCR		! FPGA, PCMCIA, USB, ext slot
196CS4BCR_D:	.long	0x24920400
197CS5ABCR_A:	.long	CS5ABCR		! Ext slot
198CS5ABCR_D:	.long	0x24920400
199CS5BBCR_A:	.long	CS5BBCR		! USB controller
200CS5BBCR_D:	.long	0x24920400
201CS6ABCR_A:	.long	CS6ABCR		! Ethernet
202CS6ABCR_D:	.long	0x24920400
203
204CS0WCR_A:	.long	CS0WCR
205CS0WCR_D:	.long	0x00000300
206CS2WCR_A:	.long	CS2WCR
207CS2WCR_D:	.long	0x00000300
208CS4WCR_A:	.long	CS4WCR
209CS4WCR_D:	.long	0x00000300
210CS5AWCR_A:	.long	CS5AWCR
211CS5AWCR_D:	.long	0x00000300
212CS5BWCR_A:	.long	CS5BWCR
213CS5BWCR_D:	.long	0x00000300
214CS6AWCR_A:	.long	CS6AWCR
215CS6AWCR_D:	.long	0x00000300
216
217SDCR_A:		.long	SBSC_SDCR
218SDCR_D:		.long	0x00020809
219SDWCR_A:	.long	SBSC_SDWCR
220SDWCR_D:	.long	0x00164d0d
221SDPCR_A:	.long	SBSC_SDPCR
222SDPCR_D:	.long	0x00000087
223RTCOR_A:	.long	SBSC_RTCOR
224RTCOR_D:	.long	0xA55A0034
225RTCSR_A:	.long	SBSC_RTCSR
226RTCSR_D:	.long	0xA55A0010
227SDMR3_A:	.long	0xFE500180
228SDMR3_D:	.long	0x0
229
230	.align	1
231
232SBSCR_D:	.word	0x0040
233PSCR_D:		.word	0x0000
234RWTCSR_D_1:	.word	0xA507
235RWTCSR_D_2:	.word	0xA507
236RWTCNT_D:	.word	0x5A00
237	.align	2
238
239SR_MASK_D:	.long	0xEFFFFF0F
240